公开(公告)号：US06867075B2

公开(公告)日：2005-03-15

申请号：US10378359

申请日：2003-03-03

申请人： Nobuhiko Oda ,  Shiro Nakanishi ,  Shinji Yuda ,  Tsutomu Yamada

发明人： Nobuhiko Oda ,  Shiro Nakanishi ,  Shinji Yuda ,  Tsutomu Yamada

IPC分类号： H01L27/08 ,  H01L21/318 ,  H01L21/336 ,  H01L29/786 ,  H01L21/00 ,  H01L21/84

CPC分类号： H01L29/66765 ,  H01L29/78636

摘要： On a transparent substrate to which a gate electrode is arranged, a silicon nitride film and a silicon oxide film to be gate insulating films are deposited, and further, a polycrystalline silicon film as a semiconductor film to be an active region is formed. On the polycrystalline silicon film corresponding to the gate electrode, a stopper is arranged, and a silicon oxide film and a silicon nitride film to be an interlayer insulating films are deposited so as to cover this stopper. The film thickness T0 of the stopper is set in a range of 800 angstroms to 1200 angstroms. Furthermore, the film thickness T0 of the stopper is set in the range to fulfill the following expression: T0+T1≦(T2×8000 Å) where T1 is the film thickness of the silicon oxide film and T2 is the film thickness of the silicon nitride film.

摘要翻译： 在配置有栅电极的透明基板上，淀积作为栅绝缘膜的氮化硅膜和氧化硅膜，形成作为有源区的半导体膜的多晶硅膜。 在对应于栅电极的多晶硅膜上，设置有阻挡层，并且沉积作为层间绝缘膜的氧化硅膜和氮化硅膜以覆盖该阻挡层。 挡块的膜厚度T0设定在800〜1200埃的范围内。 此外，阻挡层的膜厚度T0设定在满足以下表达式的范围内：其中，T1是氧化硅膜的膜厚度，T2是氮化硅膜的膜厚度。

公开(公告)号：US06794675B1

公开(公告)日：2004-09-21

申请号：US09532283

申请日：2000-03-23

申请人： Koji Suzuki ,  Tsutomu Yamada ,  Nobuhiko Oda ,  Toshifumi Yamaji

发明人： Koji Suzuki ,  Tsutomu Yamada ,  Nobuhiko Oda ,  Toshifumi Yamaji

IPC分类号： H01L3524

CPC分类号： H01L27/3248

摘要： In an organic electroluminescence (EL) display, a TFT (40) and an organic EL element (60) are formed on an insulating substrate (10) such as a glass substrate. The contact portion between the first electrode region (e.g. the source 43s) of the active layer (43) of the TFT (40) and the organic EL element (60) is formed of a laminated structure. The laminated structure is formed of the structure stacked in layers with p-si forming the source (43s), a refractory metal (Mo), aluminum, a refractory metal (Mo), and ITO forming the anode 61. The reliable contact between the source 43s and the anode 61 can prevent variations in brightness and early degradation in characteristic of the TFT 40 and the organic EL element 60.

摘要翻译： 在有机电致发光（EL）显示器中，在诸如玻璃基板的绝缘基板（10）上形成TFT（40）和有机EL元件（60）。 TFT（40）的有源层（43）的第一电极区域（例如源极43s）与有机EL元件（60）之间的接触部分由叠层结构形成。 叠层结构由层叠有p型的层叠结构形成，形成源极（43s），难熔金属（Mo），铝，难熔金属（Mo）和形成阳极61的ITO。 源极43s和阳极61可以防止TFT 40和有机EL元件60的亮度变化和特性的早期劣化。

公开(公告)号：US06727871B1

公开(公告)日：2004-04-27

申请号：US09679102

申请日：2000-10-04

申请人： Koji Suzuki ,  Tsutomu Yamada

发明人： Koji Suzuki ,  Tsutomu Yamada

IPC分类号： G09G330

CPC分类号： H01L27/3244 ,  H01L27/3281 ,  H01L51/5209 ,  H01L2251/558

摘要： Side faces of anodes have a tapered incline that becomes broader toward a lower layer. Thus, an emissive element layer is smoothly formed on the anodes making it possible to prevent field contraction of the electric field. An EL display apparatus having long life and high yield is provided by preventing the emissive element layer from rupturing between an anode and a cathode and by preventing concentration of the electric field at an upper edge of the anode facing the cathode and localized deterioration in the emissive element layer.

公开(公告)号：US06703992B1

公开(公告)日：2004-03-09

申请号：US09670680

申请日：2000-09-27

申请人： Tsutomu Yamada

发明人： Tsutomu Yamada

IPC分类号： G09G330

CPC分类号： H01L27/3244 ,  H01L27/3276

摘要： In an active matrix type EL device, a semiconductor layer (intersection protective film F1, F2, F3, F4) is inserted between lines at an intersection of a gate line GL and a data line DL; an intersection of the gate line GL and a power source line VL; an intersection of a storage capacitor line CL and the data line DL; and an intersection of the storage capacitor line CL and the power source line VL for inter-line insulation. No impurities are doped in the regions corresponding to these intersections CR1˜CR4, to thereby maintain high resistance. The intersection protective films are integrally formed for the intersections CR1 and CR2 and for the intersections CR3 and CR4 and extend over the respective two intersections. With the above-described structure, it is possible to prevent short circuit or deterioration of voltage withstanding characteristics at the intersections on the panel where lines intersect, without a drastic increase in the number of processes.

摘要翻译： 在有源矩阵型EL器件中，半导体层（交叉保护膜F1，F2，F3，F4）插入在栅极线GL和数据线DL的交点处的线之间; 栅极线GL与电源线VL的交点; 存储电容线CL与数据线DL的交点; 以及保持电容线CL和用于线间绝缘的电源线VL的交点。 在对应于这些交点CR1〜CR4的区域中不掺杂杂质，从而保持高电阻。 相交保护膜为交点CR1和CR2以及交叉点CR3和CR4整体形成，并在相应的两个交点上延伸。 利用上述结构，可以防止线路相交的面板上的交点处的电压耐受特性的短路或劣化，而不会急剧增加处理次数。

公开(公告)号：US06686215B2

公开(公告)日：2004-02-03

申请号：US09820139

申请日：2001-03-28

申请人： Tsutomu Yamada

发明人： Tsutomu Yamada

IPC分类号： H01L2100

CPC分类号： H01L27/1288 ,  H01L27/12 ,  H01L27/1214 ,  H01L27/3211 ,  H01L27/3244 ,  H01L51/0011 ,  H01L2251/558

摘要： An emissive element layer (65) composed of an organic compound is formed on an anode (61) of an organic EL element or the like, using an evaporation mask (150) in which the width d of an opening (151) and the thickness h of the mask (150) satisfy the relationship h>n×d, Where n>1, and more preferably 1

摘要翻译： 在有机EL元件等的阳极（61）上，使用其中开口（151）的宽度d和厚度（151）的蒸发掩模（150）形成由有机化合物构成的发射元件层（65） 掩模（150）的h满足关系h> nxd，其中n≥1，更优选1

公开(公告)号：US06613618B1

公开(公告)日：2003-09-02

申请号：US09542200

申请日：2000-04-04

申请人： Shiro Nakanishi ,  Tsutomu Yamada

发明人： Shiro Nakanishi ,  Tsutomu Yamada

IPC分类号： H01L2184

CPC分类号： H01L29/66757 ,  H01L29/66765 ,  H01L29/78675 ,  H01L29/78678

摘要： A thin-film transistor is provided in which the thickness of the insulating film is optimized. A gate electrode is formed on a transparent substrate. A silicon nitride film and a silicon oxide film, acting as a gate insulating film, are formed over the transparent substrate. A polycrystalline silicon film, being a semiconductor film, is formed acting as an active region. A stopper is formed on the polycrystalline silicon film corresponding to the gate electrode. A silicon oxide film and a silicon nitride film, acting as an interlayer insulating film, are deposited as to cover the stopper region. The total film thickness T1 of the stopper and the silicon oxide film is formed to be thinner than (the thickness T2 of the silicon nitride film×8000 Å)½. This structure allows hydrogen atoms to be sufficiently supplied from the silicon nitride film into the polycrystalline silicon film via the stopper and the silicon oxide film, so that crystalline defects in the polycrystalline silicon film can be filled with the hydrogen atoms.

摘要翻译： 提供了薄膜晶体管，其中绝缘膜的厚度被优化。 在透明基板上形成栅电极。 在透明基板上形成用作栅极绝缘膜的氮化硅膜和氧化硅膜。 作为半导体膜的多晶硅膜被形成为起主动区域的作用。 在与栅电极相对应的多晶硅膜上形成止动件。 作为层间绝缘膜的氧化硅膜和氮化硅膜被沉积以覆盖阻挡区域。 阻挡层和氧化硅膜的总膜厚T1形成为比（氮化硅膜的厚度T2）薄。 这种结构使得氢原子能够通过阻挡层和氧化硅膜从氮化硅膜充分供给到多晶硅膜中，从而可以用氢原子填充多晶硅膜中的晶体缺陷。

公开(公告)号：US06522079B1

公开(公告)日：2003-02-18

申请号：US09672929

申请日：2000-09-28

申请人： Tsutomu Yamada

发明人： Tsutomu Yamada

IPC分类号： G09G310

CPC分类号： H01L27/3276

摘要： A single shared line (VLc) is provided as a power source line (VL) between two display pixels disposed adjoining each other in a row direction. Such a layout with the shared line (VLc) makes it possible to set the width of the shared line (VLc) equal to the sum of twice the width (Wd) of the power source line and the space (Ws) between the lines, even with the area of a single pixel is the same as in a conventional design. As a result, an increase in line resistance of the power source line can be suppressed, and variation in display luminance in accordance with the distance from a power source terminal due to a voltage drop can be reliably reduced.

摘要翻译： 提供单个共享线路（VLc）作为在行方向上彼此相邻布置的两个显示像素之间的电源线（VL）。 具有共享线路（VLc）的布局使得可以将共享线路（VLc）的宽度设置为等于电源线路宽度（Wd）和线路之间的空间（Ws）的两倍的总和， 即使单个像素的面积与常规设计中的相同。 结果，可以抑制电源线的线路电阻的增加，并且可以可靠地降低由于电压降引起的与电源端子的距离的显示亮度的变化。

公开(公告)号：US06469318B2

公开(公告)日：2002-10-22

申请号：US09966018

申请日：2001-09-28

申请人： Tsutomu Yamada ,  Katsuya Anzai

发明人： Tsutomu Yamada ,  Katsuya Anzai

IPC分类号： H01L2904

CPC分类号： H01L21/02686 ,  H01L21/02691 ,  H01L21/2026

摘要： Thin film transistors TFT2a and TFT2b for driving elements are formed in parallel between a power source line (16) and an organic EL element (60), and active layers (12) of the transistors TFT2a and TFT2b are spaced apart in a scanning direction of a laser used for annealing for polycrystallization. As a result, the annealing conditions for the transistors TFT2a and TFT2b will not be exactly the same, thereby reducing the chance of a same problem being caused in both transistors TFT2a and TFT2b.

摘要翻译： 在电源线（16）和有机EL元件（60）之间并联形成用于驱动元件的薄膜晶体管TFT2a和TFT2b，晶体管TFT2a和TFT2b的有源层（12）在扫描方向 用于多结晶退火的激光。 结果，晶体管TFT2a和TFT2b的退火条件将不完全相同，从而减少在晶体管TFT2a和TFT2b两者中引起相同问题的机会。

公开(公告)号：US06393509B2

公开(公告)日：2002-05-21

申请号：US09932973

申请日：2001-08-21

申请人： Tsutomu Yamada ,  Kenichi Kurosawa ,  Yasuo Kaminaga ,  Kouji Masui ,  Akihiro Ohashi

发明人： Tsutomu Yamada ,  Kenichi Kurosawa ,  Yasuo Kaminaga ,  Kouji Masui ,  Akihiro Ohashi

IPC分类号： G06F1300

CPC分类号： G06F13/4081 ,  G06F1/189 ,  Y02D10/14 ,  Y02D10/151

摘要： There is provided an input/output device having of not exerting any adverse influence on other expansion devices connected to a system bus at the time of insertion or removal. An expansion device 800 comprises an electronic circuit 400 and a MOS switch 300, and is connected to a system bus (BUS) via a connector having long and short pins. The expansion device 800 two power supply systems, namely a stable power supply 250 and an unstable power supply 260. At the time of insertion or removal of the expansion device 800, power is provided to the MOS switch 300 and a high impedance maintaining circuit from the stable power supply via a pair of long pins, so as to reliably place the MOS switch 300 in a high impedance state, inside the expansion device the high impedance maintaining circuit 350 drives an open/close control terminal, and power is provided to the electronic circuit 400 from the unstable power supply 260. At the time of insertion or removal, adverse influence is not exerted on the signal transmission on the system bus, and effects of load variation on the main power supply are reduced.

摘要翻译： 提供了一种输入/输出装置，其在插入或移除时对连接到系统总线的其它扩展装置没有任何不利影响。扩展装置800包括电子电路400和MOS开关300，并且被连接 通过具有长和短引脚的连接器连接到系统总线（BUS）。 膨胀装置800是两个电源系统，即稳定的电源250和不稳定的电源260.在插入或移除扩展装置800时，向MOS开关300提供电力和高阻抗保持电路 通过一对长引脚稳定供电，为了可靠地将MOS开关300置于高阻抗状态，高阻抗保持电路350在扩展装置的内部驱动开/关控制端子，并且向 来自不稳定电源260的电子电路400.在插入或移除时，不会对系统总线上的信号传输产生不利影响，并且降低对主电源的负载变化的影响。

公开(公告)号：US06274414B1

公开(公告)日：2001-08-14

申请号：US08911505

申请日：1997-08-14

申请人： Hidenori Ogata ,  Ken Wakita ,  Kiyoshi Yoneda ,  Yoshihiro Morimoto ,  Tsutomu Yamada ,  Kazuhiro Imao ,  Takashi Kuwahara

发明人： Hidenori Ogata ,  Ken Wakita ,  Kiyoshi Yoneda ,  Yoshihiro Morimoto ,  Tsutomu Yamada ,  Kazuhiro Imao ,  Takashi Kuwahara

IPC分类号： H01L21324

CPC分类号： H01L21/02686 ,  H01L21/02532 ,  H01L21/02691 ,  H01L21/2026 ,  H01L21/268 ,  H01L27/1296 ,  H01L29/66757 ,  H01L29/78675

摘要： For obtaining p-Si by irradiating a laser beam to an a-Si layer to polycrystallize, an energy level in a region to be irradiated by the laser beam is set such that a level at the rear area of the region along a scan direction of the laser beam is lower than that at the front area or the center area of the region. The energy level at the front area or the center area of the region is set such that it is substantially equal to or more than the upper limit energy level which maximizes a grain size of the p-Si obtained. since an energy profile is set as described above, when the laser beam is scanned on the a-Si layer, an irradiated energy of the laser on the region is gradually lowered from the upper limit as the laser beam passes through, which allows the semiconductor layer to be annealed within an optimal energy level during the latter half of the annealing process.

摘要翻译： 为了通过将激光束照射到a-Si层进行多晶化来获得p-Si，将由激光束照射的区域中的能级设定为使沿着扫描方向的区域的后部区域的电平 激光束比区域前区域或中心区域低。 该区域的前部区域或中心区域的能级被设定为使得所获得的p-Si的粒径最大化的上限能级基本上等于或大于该能级。 由于如上所述设定能量分布，当在a-Si层上扫描激光束时，该区域上的激光的照射能量随着激光束通过而从上限逐渐降低，这允许半导体 在退火过程的后半期间在最佳能级内退火的层。