公开(公告)号：US06797651B2

公开(公告)日：2004-09-28

申请号：US10080424

申请日：2002-02-22

申请人： Takashi Hagino ,  Kazuhiro Imao ,  Ken Wakita ,  Toshio Monzen ,  Hidenori Ogata ,  Shiro Nakanishi ,  Yoshihiro Morimoto

发明人： Takashi Hagino ,  Kazuhiro Imao ,  Ken Wakita ,  Toshio Monzen ,  Hidenori Ogata ,  Shiro Nakanishi ,  Yoshihiro Morimoto

IPC分类号： H01L2126

CPC分类号： H01L21/02675 ,  H01L21/02532 ,  H01L21/02686 ,  H01L21/2026 ,  H01L21/268

摘要： A laser annealing apparatus is provided in which laser light is irradiated onto an amorphous semiconductor layer placed inside an annealing chamber through a chamber window, thereby poly-crystallizing the amorphous semiconductor film. Inside the annealing chamber a low degree vacuum (about 1.3×103 Pa to about 1.3 Pa) is maintained at a room temperature. An inert gas such as nitrogen, hydrogen, or argon is introduced into the atmosphere while maintaining the low degree vacuum. As a result, the surface smoothness of the polycrystalline semiconductor layer is comparable to that resulting from high degree vacuum annealing, while, unlike high degree vacuum annealing, there is less contamination of the chamber window and productivity is improved.

摘要翻译： 提供一种激光退火装置，其中激光照射到通过室窗放置在退火室内部的非晶半导体层上，从而使非晶半导体膜多晶化。 在退火室内，将低度真空度（约1.3×10 3 Pa至约1.3Pa）保持在室温。 将惰性气体如氮气，氢气或氩气引入气氛中同时保持低度真空度。 结果，多晶半导体层的表面平滑度与高度真空退火得到的表面平滑度相当，而与高度真空退火不同，室窗口的污染较少，生产率提高。

公开(公告)号：US5721601A

公开(公告)日：1998-02-24

申请号：US532484

申请日：1995-09-22

申请人： Toshifumi Yamaji ,  Kou Masahara ,  Nobuhiko Oda ,  Koji Suzuki ,  Shiro Nakanishi ,  Hisashi Abe ,  Kiyoshi Yoneda ,  Yoshihiro Morimoto

发明人： Toshifumi Yamaji ,  Kou Masahara ,  Nobuhiko Oda ,  Koji Suzuki ,  Shiro Nakanishi ,  Hisashi Abe ,  Kiyoshi Yoneda ,  Yoshihiro Morimoto

IPC分类号： G02F1/1343 ,  G02F1/1333 ,  G02F1/136 ,  G02F1/1362 ,  G02F1/1368 ,  H01L21/336 ,  H01L29/786

CPC分类号： G02F1/136227 ,  G02F2001/133357

摘要： A liquid crystal display unit is described, which includes a first substrate, a second substrate opposing to the first substrate, pixel driving elements, first and second insulation layers, a planarizing film and a liquid crystal layer. The pixel driving elements are disposed on the first substrate and between the first and second substrates. The first insulation layer is deposited over the first substrate and the pixel driving elements. The planarizing film is formed on the first insulation layer. This planarizing film provides a substantially flat surface over the first substrate to minimize a height of a step present between an area corresponding to each pixel driving element and an area locating adjacent to the pixel driving element on the first substrate. The second insulation layer is formed on the planarizing film. The display electrodes are formed on the second insulation layer and electrically connected to the pixel driving elements, respectively. The liquid crystal layer is located between the first substrate and said second substrate.

摘要翻译： 描述了一种液晶显示单元，其包括第一基板，与第一基板相对的第二基板，像素驱动元件，第一和第二绝缘层，平坦化膜和液晶层。 像素驱动元件设置在第一基板上并且在第一和第二基板之间。 第一绝缘层沉积在第一衬底和像素驱动元件上。 平坦化膜形成在第一绝缘层上。 该平坦化膜在第一基板上提供基本上平坦的表面，以使在与每个像素驱动元件相对应的区域和与第一基板上的像素驱动元件相邻定位的区域之间存在的台阶的高度最小化。 第二绝缘层形成在平坦化膜上。 显示电极分别形成在第二绝缘层上并与像素驱动元件电连接。 液晶层位于第一基板和第二基板之间。

公开(公告)号：US06867075B2

公开(公告)日：2005-03-15

申请号：US10378359

申请日：2003-03-03

申请人： Nobuhiko Oda ,  Shiro Nakanishi ,  Shinji Yuda ,  Tsutomu Yamada

发明人： Nobuhiko Oda ,  Shiro Nakanishi ,  Shinji Yuda ,  Tsutomu Yamada

IPC分类号： H01L27/08 ,  H01L21/318 ,  H01L21/336 ,  H01L29/786 ,  H01L21/00 ,  H01L21/84

CPC分类号： H01L29/66765 ,  H01L29/78636

摘要： On a transparent substrate to which a gate electrode is arranged, a silicon nitride film and a silicon oxide film to be gate insulating films are deposited, and further, a polycrystalline silicon film as a semiconductor film to be an active region is formed. On the polycrystalline silicon film corresponding to the gate electrode, a stopper is arranged, and a silicon oxide film and a silicon nitride film to be an interlayer insulating films are deposited so as to cover this stopper. The film thickness T0 of the stopper is set in a range of 800 angstroms to 1200 angstroms. Furthermore, the film thickness T0 of the stopper is set in the range to fulfill the following expression: T0+T1≦(T2×8000 Å) where T1 is the film thickness of the silicon oxide film and T2 is the film thickness of the silicon nitride film.

摘要翻译： 在配置有栅电极的透明基板上，淀积作为栅绝缘膜的氮化硅膜和氧化硅膜，形成作为有源区的半导体膜的多晶硅膜。 在对应于栅电极的多晶硅膜上，设置有阻挡层，并且沉积作为层间绝缘膜的氧化硅膜和氮化硅膜以覆盖该阻挡层。 挡块的膜厚度T0设定在800〜1200埃的范围内。 此外，阻挡层的膜厚度T0设定在满足以下表达式的范围内：其中，T1是氧化硅膜的膜厚度，T2是氮化硅膜的膜厚度。

公开(公告)号：US06815272B2

公开(公告)日：2004-11-09

申请号：US10008389

申请日：2001-11-06

申请人： Nobuhiko Oda ,  Toshifumi Yamaji ,  Shiro Nakanishi ,  Yoshihiro Morimoto ,  Kiyoshi Yoneda

发明人： Nobuhiko Oda ,  Toshifumi Yamaji ,  Shiro Nakanishi ,  Yoshihiro Morimoto ,  Kiyoshi Yoneda

IPC分类号： H01L2100

CPC分类号： H01L29/66765 ,  H01L27/12 ,  H01L27/1248 ,  H01L29/78621 ,  H01L29/78678

摘要： In a bottom gate-type thin-film transistor manufacturing method, after ion doping, an ion stopper is removed. The ion stopper does not remain in the interlayer insulating film lying immediately above the gate electrode. The thin-film transistor has such a structure that no ion stopper, and the interlayer insulating layer is in direct contact with at least the channel region of the semiconductor layer. The impurity concentration in the vicinity of the interface between the interlayer insulating film and the semiconductor layer 4 is 1018 atoms/cc or less. This structure can prevent the back channel phenomenon and reduce variations in characteristic resulting from variations in manufacturing.

摘要翻译： 在底栅型薄膜晶体管制造方法中，在离子掺杂之后，去除离子塞。 离子限制器不会残留在位于栅电极正上方的层间绝缘膜中。 薄膜晶体管具有这样的结构：离子阻挡层和层间绝缘层至少与半导体层的沟道区域直接接触。 层间绝缘膜和半导体层4之间的界面附近的杂质浓度为10 18原子/ cc以下。 这种结构可以防止反向通道现象，并减少由制造变化引起的特性变化。

公开(公告)号：US06613618B1

公开(公告)日：2003-09-02

申请号：US09542200

申请日：2000-04-04

申请人： Shiro Nakanishi ,  Tsutomu Yamada

发明人： Shiro Nakanishi ,  Tsutomu Yamada

IPC分类号： H01L2184

CPC分类号： H01L29/66757 ,  H01L29/66765 ,  H01L29/78675 ,  H01L29/78678

摘要： A thin-film transistor is provided in which the thickness of the insulating film is optimized. A gate electrode is formed on a transparent substrate. A silicon nitride film and a silicon oxide film, acting as a gate insulating film, are formed over the transparent substrate. A polycrystalline silicon film, being a semiconductor film, is formed acting as an active region. A stopper is formed on the polycrystalline silicon film corresponding to the gate electrode. A silicon oxide film and a silicon nitride film, acting as an interlayer insulating film, are deposited as to cover the stopper region. The total film thickness T1 of the stopper and the silicon oxide film is formed to be thinner than (the thickness T2 of the silicon nitride film×8000 Å)½. This structure allows hydrogen atoms to be sufficiently supplied from the silicon nitride film into the polycrystalline silicon film via the stopper and the silicon oxide film, so that crystalline defects in the polycrystalline silicon film can be filled with the hydrogen atoms.

摘要翻译： 提供了薄膜晶体管，其中绝缘膜的厚度被优化。 在透明基板上形成栅电极。 在透明基板上形成用作栅极绝缘膜的氮化硅膜和氧化硅膜。 作为半导体膜的多晶硅膜被形成为起主动区域的作用。 在与栅电极相对应的多晶硅膜上形成止动件。 作为层间绝缘膜的氧化硅膜和氮化硅膜被沉积以覆盖阻挡区域。 阻挡层和氧化硅膜的总膜厚T1形成为比（氮化硅膜的厚度T2）薄。 这种结构使得氢原子能够通过阻挡层和氧化硅膜从氮化硅膜充分供给到多晶硅膜中，从而可以用氢原子填充多晶硅膜中的晶体缺陷。

公开(公告)号：US06191452B1

公开(公告)日：2001-02-20

申请号：US09162836

申请日：1998-09-29

申请人： Nobuhiko Oda ,  Shiro Nakanishi ,  Shinji Yuda ,  Tsutomu Yamada

发明人： Nobuhiko Oda ,  Shiro Nakanishi ,  Shinji Yuda ,  Tsutomu Yamada

IPC分类号： H01L2900

CPC分类号： H01L29/66765 ,  H01L29/78636

摘要： On a transparent substrate to which a gate electrode is arranged, a silicon nitride film and a silicon oxide film to be gate insulating films are deposited, and further, a polycrystalline silicon film as a semiconductor film to be an active region is formed. On the polycrystalline silicon film corresponding to the gate electrode, a stopper is arranged, and a silicon oxide film and a silicon nitride film to be an interlayer insulating films are deposited so as to cover this stopper. The film thickness T0 of the stopper is set in a range of 800 angstroms to 1200 angstroms. Furthermore, the film thickness T0 of the stopper is set in the range to fulfill the following expression: T0+T1≦(T2×8000 Å)½ where T1 is the film thickness of the silicon oxide film and T2 is the film thickness of the silicon nitride film.

摘要翻译： 在配置有栅电极的透明基板上，淀积作为栅绝缘膜的氮化硅膜和氧化硅膜，形成作为有源区的半导体膜的多晶硅膜。 在对应于栅电极的多晶硅膜上，设置有阻挡层，并且沉积作为层间绝缘膜的氧化硅膜和氮化硅膜以覆盖该阻挡层。 挡块的膜厚度T0设定在800〜1200埃的范围内。 此外，阻挡层的膜厚度T0设定在满足以下表达式的范围内：其中，T1是氧化硅膜的膜厚度，T2是氮化硅膜的膜厚度。

公开(公告)号：US07045818B2

公开(公告)日：2006-05-16

申请号：US10818425

申请日：2004-04-05

申请人： Yushi Jinno ,  Shiro Nakanishi ,  Kyoko Hirai ,  Tsutomu Yamada ,  Yoshihiro Morimoto ,  Kiyoshi Yoneda

发明人： Yushi Jinno ,  Shiro Nakanishi ,  Kyoko Hirai ,  Tsutomu Yamada ,  Yoshihiro Morimoto ,  Kiyoshi Yoneda

IPC分类号： H01L31/20 ,  H01L29/04 ,  H01L21/00

CPC分类号： H01L27/127 ,  H01L27/1214 ,  H01L29/66765 ,  H01L29/78621

摘要： In a fabrication process of a semiconductor device for use in a TFT liquid crystal display system, before the start of crystallizing amorphous silicon (a-Si), dehydrogenation annealing is carried out to not only decrease the density of hydrogen in the p-Si film (13) to 5×1020 atoms/cm3 at most but also to prevent crystallization of the a-Si film (13) being obstructed due to possible excessive hydrogen remaining in the film. With the p-Si film (13) covered with an interlayer insulation film (15) in the form of a plasma nitride film, annealing is then carried out in nitrogen atmosphere at a temperature of 350° C. to 400° C. for one to three hours, more preferably 400° C. for two hours. The result is that hydrogen atoms in the p-Si film (13) efficiently terminate dangling bonds of the film and hence do not become excessive, thus improving the electrical characteristics of the semiconductor device.

摘要翻译： 在用于TFT液晶显示系统的半导体器件的制造工艺中，在开始结晶非晶硅（a-Si）之前，进行脱氢退火以不仅降低p-Si膜中的氢的密度 （13）至5×10 20原子/ cm 3以上，同时也防止由于可能存在过剩氢气而导致的阻塞a-Si膜（13）的结晶 电影。 在用等离子体氮化物膜形式的层间绝缘膜（15）覆盖的p-Si膜（13）上，然后在氮气气氛中在350℃至400℃的温度下进行退火，一个 至3小时，更优选400℃2小时。 结果是，p-Si膜（13）中的氢原子有效地终止膜的悬挂键，因此不会变得过大，从而改善了半导体器件的电特性。

公开(公告)号：US20050042809A1

公开(公告)日：2005-02-24

申请号：US10946037

申请日：2004-09-21

申请人： Nobuhiko Oda ,  Toshifumi Yamaji ,  Shiro Nakanishi ,  Yoshihiro Morimoto ,  Kiyoshi Yoneda

发明人： Nobuhiko Oda ,  Toshifumi Yamaji ,  Shiro Nakanishi ,  Yoshihiro Morimoto ,  Kiyoshi Yoneda

IPC分类号： G02F1/136 ,  G02F1/00 ,  G02F1/1368 ,  G09F9/30 ,  H01L21/00 ,  H01L21/336 ,  H01L21/77 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/12 ,  H01L29/04 ,  H01L29/786

CPC分类号： H01L29/66765 ,  H01L27/12 ,  H01L27/1248 ,  H01L29/78621 ,  H01L29/78678

摘要： In a bottom gate-type thin-film transistor manufacturing method, after ion doping, an ion stopper (55) is removed. The ion stopper (55) does not remain in the interlayer insulating film (8) lying immediately above the gate electrode. The thin-film transistor has such a structure that no ion stopper (55), and the interlayer insulating layer is in direct contact with at least the channel region of the semiconductor layer (4). The impurity concentration in the vicinity of the interface between the interlayer insulating film and the semiconductor layer 4 is 1018 atoms/cc or less. This structure can prevent the back channel phenomenon and reduce variations in characteristic resulting from variations in manufacturing.

公开(公告)号：US20050035348A1

公开(公告)日：2005-02-17

申请号：US10945233

申请日：2004-09-20

申请人： Nobuhiko Oda ,  Toshifumi Yamaji ,  Shiro Nakanishi ,  Yoshihiro Morimoto ,  Kiyoshi Yoneda

发明人： Nobuhiko Oda ,  Toshifumi Yamaji ,  Shiro Nakanishi ,  Yoshihiro Morimoto ,  Kiyoshi Yoneda

IPC分类号： G02F1/136 ,  G02F1/00 ,  G02F1/1368 ,  G09F9/30 ,  H01L21/00 ,  H01L21/336 ,  H01L21/77 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/12 ,  H01L29/04 ,  H01L29/786

CPC分类号： H01L29/66765 ,  H01L27/12 ,  H01L27/1248 ,  H01L29/78621 ,  H01L29/78678

摘要： In a bottom gate-type thin-film transistor manufacturing method, after ion doping, an ion stopper (55) is removed. The ion stopper (55) does not remain in the interlayer insulating film (8) lying immediately above the gate electrode. The thin-film transistor has such a structure that no ion stopper (55), and the interlayer insulating layer is in direct contact with at least the channel region of the semiconductor layer (4). The impurity concentration in the vicinity of the interface between the interlayer insulating film and the semiconductor layer 4 is 1018 atoms/cc or less. This structure can prevent the back channel phenomenon and reduce variations in characteristic resulting from variations in manufacturing.

摘要翻译： 在底栅型薄膜晶体管制造方法中，在离子掺杂之后，去除离子塞（55）。 离子限制器（55）不会留在位于栅电极正上方的层间绝缘膜（8）中。 薄膜晶体管具有这样的结构：离子阻挡层（55）和层间绝缘层至少与半导体层（4）的沟道区域直接接触。 层间绝缘膜和半导体层4之间的界面附近的杂质浓度为10 18原子/ cc以下。 这种结构可以防止反向通道现象，并减少由制造变化引起的特性变化。

公开(公告)号：US06750086B2

公开(公告)日：2004-06-15

申请号：US09049353

申请日：1998-03-27

申请人： Yushi Jinno ,  Shiro Nakanishi ,  Kyoko Hirai ,  Tsutomu Yamada ,  Yoshihiro Morimoto ,  Kiyoshi Yoneda

发明人： Yushi Jinno ,  Shiro Nakanishi ,  Kyoko Hirai ,  Tsutomu Yamada ,  Yoshihiro Morimoto ,  Kiyoshi Yoneda

IPC分类号： H01L2100

CPC分类号： H01L27/127 ,  H01L27/1214 ,  H01L29/66765 ,  H01L29/78621

摘要： In a fabrication process of a semiconductor device for use in a TFT liquid crystal display system, before the start of crystallizing amorphous silicon (a-Si), dehydrogenation annealing is carried out to not only decrease the density of hydrogen in the p-Si film (13) to 5×1020 atoms/cm3 at most but also to prevent crystallization of the a-Si film (13) being obstructed due to possible excessive hydrogen remaining in the film. With the p-Si film (13) covered with an interlayer insulation film (15) in the form of a plasma nitride film, annealing is then carried out in nitrogen atmosphere at a temperature of 350° C. to 400° C. for one to three hours, more preferably 400° C. for two hours. The result is that hydrogen atoms in the p-Si film (13) efficiently terminate dangling bonds of the film and hence do not become excessive, thus improving the electrical characteristics of the semiconductor device.

摘要翻译： 在用于TFT液晶显示系统的半导体器件的制造工艺中，在开始结晶非晶硅（a-Si）之前，进行脱氢退火以不仅降低p-Si膜中的氢的密度 （13）〜5×10 20原子/ cm 3以下，同时也防止由于膜中剩余的氢过量而导致的阻塞a-Si膜的结晶化。 在用等离子体氮化物膜形式的层间绝缘膜（15）覆盖的p-Si膜（13）上，然后在氮气气氛中在350℃至400℃的温度下进行退火，一个 至3小时，更优选400℃2小时。 结果是，p-Si膜（13）中的氢原子有效地终止膜的悬挂键，因此不会变得过大，从而改善了半导体器件的电特性。