公开(公告)号：US06555419B2

公开(公告)日：2003-04-29

申请号：US09746253

申请日：2000-12-21

申请人： Nobuhiko Oda ,  Shiro Nakanishi ,  Shinji Yuda ,  Tsutomu Yamada

发明人： Nobuhiko Oda ,  Shiro Nakanishi ,  Shinji Yuda ,  Tsutomu Yamada

IPC分类号： H01L2100

CPC分类号： H01L29/66765 ,  H01L29/78636

摘要： On a transparent substrate to which a gate electrode is arranged, a silicon nitride film and a silicon oxide film to be gate insulating films are deposited, and further, a polycrystalline silicon film as a semiconductor film to be an active region is formed. On the polycrystalline silicon film corresponding to the gate electrode, a stopper is arranged, and a silicon oxide film and a silicon nitride film to be an interlayer insulating films are deposited so as to cover this stopper. The film thickness T0 of the stopper is set in a range of 800 angstroms to 1200 angstroms. Furthermore, the film thickness T0 of the stopper is set in the range to fulfill the following expression: T0+T1≦(T2×8000 Å)½ where T1 is the film thickness of the silicon oxide film and T2 is the film thickness of the silicon nitride film.

摘要翻译： 在配置有栅电极的透明基板上，淀积作为栅绝缘膜的氮化硅膜和氧化硅膜，形成作为有源区的半导体膜的多晶硅膜。 在对应于栅电极的多晶硅膜上，设置有阻挡层，并且沉积作为层间绝缘膜的氧化硅膜和氮化硅膜以覆盖该阻挡层。 挡块的膜厚度T0设定在800〜1200埃的范围内。 此外，阻挡层的膜厚度T0设定在满足以下表达式的范围内：其中，T1是氧化硅膜的膜厚度，T2是氮化硅膜的膜厚度。

公开(公告)号：US06867075B2

公开(公告)日：2005-03-15

申请号：US10378359

申请日：2003-03-03

申请人： Nobuhiko Oda ,  Shiro Nakanishi ,  Shinji Yuda ,  Tsutomu Yamada

发明人： Nobuhiko Oda ,  Shiro Nakanishi ,  Shinji Yuda ,  Tsutomu Yamada

IPC分类号： H01L27/08 ,  H01L21/318 ,  H01L21/336 ,  H01L29/786 ,  H01L21/00 ,  H01L21/84

CPC分类号： H01L29/66765 ,  H01L29/78636

摘要： On a transparent substrate to which a gate electrode is arranged, a silicon nitride film and a silicon oxide film to be gate insulating films are deposited, and further, a polycrystalline silicon film as a semiconductor film to be an active region is formed. On the polycrystalline silicon film corresponding to the gate electrode, a stopper is arranged, and a silicon oxide film and a silicon nitride film to be an interlayer insulating films are deposited so as to cover this stopper. The film thickness T0 of the stopper is set in a range of 800 angstroms to 1200 angstroms. Furthermore, the film thickness T0 of the stopper is set in the range to fulfill the following expression: T0+T1≦(T2×8000 Å) where T1 is the film thickness of the silicon oxide film and T2 is the film thickness of the silicon nitride film.

摘要翻译： 在配置有栅电极的透明基板上，淀积作为栅绝缘膜的氮化硅膜和氧化硅膜，形成作为有源区的半导体膜的多晶硅膜。 在对应于栅电极的多晶硅膜上，设置有阻挡层，并且沉积作为层间绝缘膜的氧化硅膜和氮化硅膜以覆盖该阻挡层。 挡块的膜厚度T0设定在800〜1200埃的范围内。 此外，阻挡层的膜厚度T0设定在满足以下表达式的范围内：其中，T1是氧化硅膜的膜厚度，T2是氮化硅膜的膜厚度。

公开(公告)号：US06191452B1

公开(公告)日：2001-02-20

申请号：US09162836

申请日：1998-09-29

申请人： Nobuhiko Oda ,  Shiro Nakanishi ,  Shinji Yuda ,  Tsutomu Yamada

发明人： Nobuhiko Oda ,  Shiro Nakanishi ,  Shinji Yuda ,  Tsutomu Yamada

IPC分类号： H01L2900

CPC分类号： H01L29/66765 ,  H01L29/78636

摘要： On a transparent substrate to which a gate electrode is arranged, a silicon nitride film and a silicon oxide film to be gate insulating films are deposited, and further, a polycrystalline silicon film as a semiconductor film to be an active region is formed. On the polycrystalline silicon film corresponding to the gate electrode, a stopper is arranged, and a silicon oxide film and a silicon nitride film to be an interlayer insulating films are deposited so as to cover this stopper. The film thickness T0 of the stopper is set in a range of 800 angstroms to 1200 angstroms. Furthermore, the film thickness T0 of the stopper is set in the range to fulfill the following expression: T0+T1≦(T2×8000 Å)½ where T1 is the film thickness of the silicon oxide film and T2 is the film thickness of the silicon nitride film.

摘要翻译： 在配置有栅电极的透明基板上，淀积作为栅绝缘膜的氮化硅膜和氧化硅膜，形成作为有源区的半导体膜的多晶硅膜。 在对应于栅电极的多晶硅膜上，设置有阻挡层，并且沉积作为层间绝缘膜的氧化硅膜和氮化硅膜以覆盖该阻挡层。 挡块的膜厚度T0设定在800〜1200埃的范围内。 此外，阻挡层的膜厚度T0设定在满足以下表达式的范围内：其中，T1是氧化硅膜的膜厚度，T2是氮化硅膜的膜厚度。

公开(公告)号：US06995048B2

公开(公告)日：2006-02-07

申请号：US10333194

申请日：2002-05-16

申请人： Kiyoshi Yoneda ,  Tsutomu Yamada ,  Shinji Yuda ,  Koji Suzuki

发明人： Kiyoshi Yoneda ,  Tsutomu Yamada ,  Shinji Yuda ,  Koji Suzuki

IPC分类号： H01L21/00 ,  H01L21/84

CPC分类号： H01L27/1288 ,  G02F1/13454 ,  G02F1/136227 ,  H01L27/1214 ,  H01L27/124 ,  H01L27/127 ,  H01L29/41733 ,  H01L29/66757 ,  H01L29/78621

摘要： A first contact hole is formed penetrating a gate insulating film, on which a gate electrode is formed and simultaneously a first contact is formed in the first contact hole. A second contact hole penetrating an interlayer insulating film is formed, and a second contact is formed in the second contact hole. A third contact hole is formed penetrating a planarization film, and an electrode is formed in the third contact hole. By using a plurality of contact holes for electrically connecting the electrode and a semiconductor film, the aspect ratio of each contact hole can be reduced, thereby achieving improvement in yield, high-level integration due to a reduction in difference in area between upper and bottom surfaces of the contact, and other advantageous improvements.

摘要翻译： 穿过栅极绝缘膜的第一接触孔形成栅电极，同时在第一接触孔中形成第一接触。 形成贯穿层间绝缘膜的第二接触孔，在第二接触孔中形成第二接触。 形成穿透平坦化膜的第三接触孔，并且在第三接触孔中形成电极。 通过使用用于电连接电极和半导体膜的多个接触孔，可以减小每个接触孔的纵横比，从而实现产量的提高，由于上下面积之间的差异减小而导致的高电平整合 接触面，以及其它有利的改进。