公开(公告)号：US07015136B2

公开(公告)日：2006-03-21

申请号：US10618219

申请日：2003-07-10

申请人： Tien-I Bao ,  Shwang-Min Jeng ,  Syun-Ming Jang

发明人： Tien-I Bao ,  Shwang-Min Jeng ,  Syun-Ming Jang

IPC分类号： H01L21/302

CPC分类号： G03F7/091 ,  Y10S438/95

摘要： A method for preventing formation of photoresist scum. First, a substrate on which a dielectric layer is formed is provided. Next, a non-nitrogen anti-reflective layer is formed on the dielectric layer. Finally, a photoresist pattern layer is formed on the non-nitrogen anti-reflective layer. During the formation of the photoresist pattern layer, the non-nitrogen anti-reflective layer does not react with the photoresist pattern layer, thus not forming photoresist scum. This prevents undesired etching profile and critical dimension (CD) change due to presence of photoresist scum. The non-nitrogen anti-reflective layer can be silicon-rich oxide (SiOx) or hydrocarbon-containing silicon-rich oxide (SiOxCy:H).

摘要翻译： 防止光刻胶浮渣形成的方法。 首先，提供形成介电层的基板。 接下来，在电介质层上形成非氮抗反射层。 最后，在非氮抗反射层上形成光刻胶图形层。 在形成光致抗蚀剂图案层期间，非氮抗反射层不与光致抗蚀剂图案层反应，因此不形成光致抗蚀剂浮渣。 这防止由于存在光致抗蚀剂浮渣而引起的不期望的蚀刻轮廓和临界尺寸（CD）变化。 非氮抗反射层可以是富氧氧化物（SiO 2）或含烃的富含氧的氧化物（SiO x x C y） SUB>：H）。

公开(公告)号：US20060051947A1

公开(公告)日：2006-03-09

申请号：US10936272

申请日：2004-09-07

申请人： Simon Lin ,  Syun-Ming Jang ,  Douglas Yu

发明人： Simon Lin ,  Syun-Ming Jang ,  Douglas Yu

IPC分类号： H01L21/44

CPC分类号： H01L21/76826 ,  H01L21/76807 ,  H01L21/76814

摘要： A method for plasma treating an etched opening formed in a porous low-K material to improve barrier layer integrity including providing a substrate comprising an etched opening formed in an insulating dielectric layer including porous low-K silicon oxide according to an overlying patterned resist layer; plasma treating according to a plasma process the etched opening to remove the resist layer and increase a surface density of the insulating dielectric layer within the etched opening; and, blanket depositing a barrier layer over the etched opening.

摘要翻译： 一种用于等离子体处理形成在多孔低K材料中的蚀刻开口以改善阻挡层完整性的方法，包括提供包括形成在包括多层低K氧化硅的绝缘介电层中的蚀刻开口的基板，所述绝缘介电层根据覆盖的图案化抗蚀剂层; 根据等离子体处理等离子体处理蚀刻开口以去除抗蚀剂层并增加蚀刻开口内的绝缘介电层的表面密度; 并且在蚀刻的开口上方覆盖沉积阻挡层。

公开(公告)号：US20060027932A1

公开(公告)日：2006-02-09

申请号：US11240216

申请日：2005-09-30

申请人： Chen-Hua Yu ,  Horng-Huei Tseng ,  Syun-Ming Jang ,  Chenming Hu

发明人： Chen-Hua Yu ,  Horng-Huei Tseng ,  Syun-Ming Jang ,  Chenming Hu

IPC分类号： H01L23/48 ,  H01L23/52

CPC分类号： H01L21/76846

摘要： Composite ALD-formed diffusion barrier layers. In a preferred embodiment, a composite conductive layer is composed of a diffusion barrier layer and/or a low-resistivity metal layer formed by atomic layer deposition (ALD) lining a damascene opening in dielectrics, serving as diffusion blocking and/or adhesion improvement. The preferred composite diffusion barrier layers are dual titanium nitride layers or dual tantalum nitride layers, triply laminar of tantalum, tantalum nitride and tantalum-rich nitride, or tantalum, tantalum nitride and tantalum, formed sequentially on the opening by way of ALD.

摘要翻译： 复合ALD形成的扩散阻挡层。 在优选实施例中，复合导电层由扩散阻挡层和/或由电介质中的镶嵌开口衬底的原子层沉积（ALD）形成的低电阻金属层组成，用作扩散阻挡和/或粘附改善。 优选的复合扩散阻挡层是通过ALD在开口上依次形成的双氮化钛层或双氮化钽层，三层层状的钽，氮化钽和富钽的氮化物，或钽，氮化钽和钽。

公开(公告)号：US20060003572A1

公开(公告)日：2006-01-05

申请号：US10884719

申请日：2004-07-03

申请人： Pi-Tsung Chen ,  Keng-Chu Lin ,  Hui-Lin Chang ,  Lih-Ping Li ,  Tien-I Bao ,  Yung-Cheng Lu ,  Syun-Ming Jang

发明人： Pi-Tsung Chen ,  Keng-Chu Lin ,  Hui-Lin Chang ,  Lih-Ping Li ,  Tien-I Bao ,  Yung-Cheng Lu ,  Syun-Ming Jang

IPC分类号： H01L21/4763

CPC分类号： H01L23/53295 ,  H01L21/76801 ,  H01L21/76802 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76835 ,  H01L23/3135 ,  H01L23/3192 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device with improved resistance to delamination and method for forming the same the method including providing a semiconductor wafer comprising a metallization layer with an uppermost etch stop layer; forming at least one adhesion promoting layer on the etch stop layer; and, forming an inter-metal dielectric (IMD) layer on the at least one adhesion promoting layer.

摘要翻译： 具有改进的分层耐受性的半导体器件及其形成方法包括提供包含具有最上蚀刻停止层的金属化层的半导体晶片的方法; 在所述蚀刻停止层上形成至少一个附着促进层; 以及在所述至少一个附着促进层上形成金属间电介质（IMD）层。

公开(公告)号：US06974730B2

公开(公告)日：2005-12-13

申请号：US10739476

申请日：2003-12-17

申请人： Carlos H. Diaz ,  Yi-Ming Sheu ,  Syun-Ming Jang ,  Hun-Jan Tao ,  Fu-Liang Yang

发明人： Carlos H. Diaz ,  Yi-Ming Sheu ,  Syun-Ming Jang ,  Hun-Jan Tao ,  Fu-Liang Yang

IPC分类号： H01L21/336 ,  H01L29/786

CPC分类号： H01L29/66772 ,  H01L29/66545 ,  H01L29/66621 ,  H01L29/78621 ,  H01L29/78654

摘要： A method for forming a field effect transistor device employs a self-aligned etching of a semiconductor substrate to form a recessed channel region in conjunction with a pair of raised source/drain regions. The method also provides for forming and thermally annealing the pair of source/drain regions prior to forming a pair of lightly doped extension regions within the field effect transistor device. In accord with the foregoing features, the field effect transistor device is fabricated with enhanced performance.

摘要翻译： 用于形成场效应晶体管器件的方法采用半导体衬底的自对准蚀刻以与一对凸起的源极/漏极区域结合形成凹陷沟道区域。 该方法还提供了在场效应晶体管器件内形成一对轻掺杂的延伸区域之前，对成对的源/漏区进行形成和热退火。 根据上述特征，以增强的性能制造场效应晶体管器件。

公开(公告)号：US06962869B1

公开(公告)日：2005-11-08

申请号：US10270974

申请日：2002-10-15

申请人： Tien-I Bao ,  Hsin-Hsien Lu ,  Lih-Ping Li ,  Chung-Chi Ko ,  Aaron Song ,  Syun-Ming Jang

发明人： Tien-I Bao ,  Hsin-Hsien Lu ,  Lih-Ping Li ,  Chung-Chi Ko ,  Aaron Song ,  Syun-Ming Jang

IPC分类号： H01L21/4763 ,  H01L21/768

CPC分类号： H01L21/3105 ,  H01L21/31144 ,  H01L21/3212 ,  H01L21/76802 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76835

摘要： A method of protecting a low k dielectric layer that is preferably comprised of a material containing Si, O, C, and H is described. The dielectric layer is subjected to a gas plasma that is generated from a CXHY gas which is preferably ethylene. Optionally, hydrogen may be added to the CXHY gas. Another alternative is a two step plasma process involving a first plasma treatment of CXHY or CXHY combined with H2 and a second plasma treatment with H2. The modified dielectric layer provides improved adhesion to anti-reflective layers and to a barrier metal layer in a damascene process. The modified dielectric layer also has a low CMP rate that prevents scratch defects and an oxide recess from occurring next to the metal layer on the surface of the damascene stack. The plasma treatments are preferably done in the same chamber in which the dielectric layer is deposited.

摘要翻译： 描述了保护低k电介质层的方法，其优选由含有Si，O，C和H的材料组成。 对电介质层进行气化等离子体，该等离子体是由优选乙烯的C X H Y气产生的。 任选地，可以将氢气加入到C 1 H 2 H 2 O气体中。 另一种替代方案是涉及第一等离子体处理C X> Y Y or SUB SUB SUB SUB SUB SUB SUB SUB SUB SUB SUB SUB SUB SUB SUB SUB SUB SUB >与H 2 H 2结合，并且与H 2 2进行第二等离子体处理。 改进的介电层在镶嵌工艺中提供对抗反射层和阻挡金属层的改善的粘合性。 改进的介电层也具有低CMP速率，其防止划痕缺陷和氧化物凹陷在镶嵌层的表面上邻近金属层发生。 等离子体处理优选在沉积介电层的相同的室中进行。

公开(公告)号：US20050184288A1

公开(公告)日：2005-08-25

申请号：US10800510

申请日：2004-03-15

申请人： Tien-I Bao ,  Syun-Ming Jang

发明人： Tien-I Bao ,  Syun-Ming Jang

IPC分类号： H01L21/311 ,  H01L21/768 ,  H01L51/00

CPC分类号： H01L21/31116 ,  H01L21/76807 ,  H01L21/76829 ,  H01L21/76838

摘要： A semiconductor device having an upper level of metallization interconnected with a lower level of metallization and a method of forming the device is provided. Accordingly, the process of the invention includes capping the lower level of metallization with an thin stop layer having a thickness of less than 300 Å and preferably about 100 Å such that the etching and ashing processes of removing photoresist and intermediate portions of etch stop layer is accomplished without damage to the lower level metallization.

摘要翻译： 提供了具有与较低金属化水平互连的金属化上位的半导体器件和形成器件的方法。 因此，本发明的方法包括用厚度小于300埃，优选约为100的薄的阻挡层封盖较低级别的金属化，使得去除蚀刻和蚀刻停止层的中间部分的蚀刻和灰化过程是 完成而不损坏较低级别的金属化。

公开(公告)号：US06878621B2

公开(公告)日：2005-04-12

申请号：US10346382

申请日：2003-01-17

申请人： Zhen-Cheng Wu ,  Lain-Jong Li ,  Yung-Chen Lu ,  Syun-Ming Jang

发明人： Zhen-Cheng Wu ,  Lain-Jong Li ,  Yung-Chen Lu ,  Syun-Ming Jang

IPC分类号： H01L21/768 ,  H01L21/44 ,  H01L21/4763

CPC分类号： H01L21/76834 ,  H01L21/76832 ,  H01L21/76835 ,  H01L21/76885

摘要： A method for forming at least one barrierless, embedded metal structure comprising the following steps. A structure having a patterned dielectric layer formed thereover with at least one opening exposing at least one respective portion of the structure. Respective metal structures are formed within each respective opening. The first dielectric layer is removed to expose the top and at least a portion of the side walls of the respective at least one metal structure. A dielectric barrier layer is formed over the structure and the exposed top of the respective metal structure. A second, conformal dielectric layer is formed over the dielectric barrier layer to complete the respective barrierless at least one metal structure embedded within the second, conformal dielectric layer. The dielectric barrier layer preventing diffusion of the metal comprising the respective at least one metal structure into the second, conformal dielectric layer.

摘要翻译： 一种形成至少一个无障碍嵌入金属结构的方法，包括以下步骤。 具有形成在其上的图案化电介质层的结构，其中至少一个开口暴露出结构的至少一个相应部分。 在每个相应的开口内形成相应的金属结构。 去除第一电介质层以暴露相应的至少一个金属结构的顶部和至少一部分侧壁。 介电阻挡层形成在相应的金属结构的结构和暴露的顶部上。 在电介质阻挡层上方形成第二个保形介电层，以完成嵌入在第二保形电介质层内的相应无障碍的至少一个金属结构。 电介质阻挡层防止包含相应的至少一种金属结构的金属扩散到第二保形电介质层中。

公开(公告)号：US06815336B1

公开(公告)日：2004-11-09

申请号：US09160965

申请日：1998-09-25

申请人： Shau-Lin Shue ,  Syun-Ming Jang

发明人： Shau-Lin Shue ,  Syun-Ming Jang

IPC分类号： H01L214763

CPC分类号： H01L21/2885 ,  H01L21/3212 ,  H01L21/32134 ,  H01L21/7684

摘要： Methods are disclosed to improve the planarization of copper damascene by the steps of patterning on the copper damascene a photoresist using a reverse tone photo mask or a reverse tone photo mask of the metal lines, removing excess copper by reverse current plating or by dry or wet chemical etching, stripping the photo resist, and a subsequent chemical mechanical planarization of the copper damascene. Lastly a cap layer is applied to the planarized surface. In a variant of the disclosed method a more relaxed reverse tone photo mask of the metal lines is used, which may be more desirable for practical use. These steps provide benefits such as improved uniformity of the wafer surface, reduce the dishing of metal lines (trenches) and pads, and reduce oxide erosion.

摘要翻译： 公开了通过以下步骤来改善铜镶嵌的平面化的步骤：使用反色调光掩模或金属线的反色调光掩模在铜镶嵌光致抗蚀剂上进行图案化，通过反向电镀或通过干或湿去除多余的铜 化学蚀刻，剥离光致抗蚀剂，以及铜镶嵌件的随后的化学机械平面化。 最后，将覆盖层施加到平坦化表面。 在所公开的方法的变型中，使用金属线的更宽松的反向色调光掩模，这对于实际使用可能是更理想的。 这些步骤提供了诸如改善晶片表面的均匀性，减少金属线（沟槽）和焊盘的凹陷以及减少氧化物侵蚀的益处。

公开(公告)号：US06812069B2

公开(公告)日：2004-11-02

申请号：US10322691

申请日：2002-12-17

申请人： Tung-Ching Tseng ,  Syun-Ming Jang ,  Chih-Hsiang Yao

发明人： Tung-Ching Tseng ,  Syun-Ming Jang ,  Chih-Hsiang Yao

IPC分类号： H01L2182

CPC分类号： H01L21/7684 ,  H01L21/3212 ,  H01L23/522 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for improving CMP polishing uniformity and reducing or preventing cracking in a semiconductor wafer process surface by reducing stress concentrations adjacent to dummy features including providing a semiconductor wafer process surface including active features and dummy features formed adjacently to the active features to improve a CMP polishing uniformity said dummy features each shaped to define an enclosed area in said semiconductor wafer process surface plane comprising at least 5 corner portions; and, performing a CMP process on said semiconductor wafer process surface.

摘要翻译： 一种通过减少与虚拟特征相邻的应力集中来提高CMP抛光均匀性并减少或防止半导体晶片工艺表面中的裂纹的方法，包括提供半导体晶片工艺表面，其包括与活性特征相邻形成的活性特征和虚拟特征，以改善CMP抛光 均匀性，所述虚拟特征各自被成形为在包括至少5个角部的所述半导体晶片工艺表面中限定封闭区域; 以及在所述半导体晶片处理表面上执行CMP处理。