公开(公告)号：US07990779B2

公开(公告)日：2011-08-02

申请号：US12585540

申请日：2009-09-17

申请人： Sang-moo Choi ,  Won-joo Kim ,  Tae-hee Lee

发明人： Sang-moo Choi ,  Won-joo Kim ,  Tae-hee Lee

IPC分类号： G11C7/00

CPC分类号： G11C11/404 ,  G11C2211/4016 ,  H01L29/7841

摘要： A method of operating a semiconductor device including a memory cell of a 1-T DRAM is provided in which a gate voltage level in a hold mode is adjusted to adjust a data sensing margin of the semiconductor device.

摘要翻译： 提供一种操作包括1-T DRAM的存储单元的半导体器件的方法，其中调整保持模式中的栅极电压电平以调整半导体器件的数据感测余量。

公开(公告)号：US07847348B2

公开(公告)日：2010-12-07

申请号：US12382281

申请日：2009-03-12

申请人： Won-joo Kim ,  Sang-moo Choi ,  Tae-hee Lee

发明人： Won-joo Kim ,  Sang-moo Choi ,  Tae-hee Lee

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/7317 ,  H01L29/7841 ,  H01L29/785 ,  H01L29/78618 ,  H01L29/78654

摘要： Provided is a semiconductor apparatus including a substrate region, an active region on the substrate region, a gate pattern on the active region, and first and second impurities-doped regions along both edges of the active region that do not overlap the gate pattern. The length of the first and second impurities-doped regions in the horizontal direction may be shorter than in the vertical direction. The first and second impurities-doped regions may be formed to be narrow along both edges of the active region so as not to overlap the gate pattern.

摘要翻译： 提供了一种半导体装置，其包括衬底区域，衬底区域上的有源区域，有源区域上的栅极图案，以及不与栅极图案重叠的有源区域沿着两个边缘的第一和第二杂质掺杂区域。 第一和第二杂质掺杂区域在水平方向上的长度可以比​​在垂直方向上短。 第一和第二杂质掺杂区域可以形成为沿着有源区域的两个边缘窄，以便不与栅极图案重叠。

公开(公告)号：US20100127759A1

公开(公告)日：2010-05-27

申请号：US12591202

申请日：2009-11-12

申请人： Sang-moo Choi ,  Won-joo Kim ,  Tae-hee Lee

发明人： Sang-moo Choi ,  Won-joo Kim ,  Tae-hee Lee

IPC分类号： H03K3/01

CPC分类号： H01L27/108 ,  H01L27/10802 ,  H01L27/10844 ,  H01L29/7841 ,  H01L29/78654

摘要： Provided is a method of operating a semiconductor device, in which a gate voltage or a drain voltage is adjusted in order to add carriers to or remove carriers from a body region, thereby realizing semiconductor having a plurality of data states.

摘要翻译： 提供了一种操作半导体器件的方法，其中调整栅极电压或漏极电压以便将载体添加到身体区域或从身体区域移除载体，从而实现具有多个数据状态的半导体。

公开(公告)号：US07986545B2

公开(公告)日：2011-07-26

申请号：US12465125

申请日：2009-05-13

申请人： Tae-eung Yoon ,  Won-joo Kim ,  June-mo Koo ,  Suk-pil Kim ,  Tae-hee Lee

发明人： Tae-eung Yoon ,  Won-joo Kim ,  June-mo Koo ,  Suk-pil Kim ,  Tae-hee Lee

IPC分类号： G11C11/00

CPC分类号： G11C8/14 ,  G11C5/02 ,  G11C5/025

摘要： A non-volatile memory device having a stack structure, and a method of operating the non-volatile memory device In which the non-volatile memory device includes a plurality of variable resistors arranged in at least one layer. At least one layer selection bit line and a plurality of bit lines coupled to the plurality of the variable resistors are provided. A plurality of selection transistors coupled between the plurality of the bit lines and the plurality of the variable resistors are provided.

摘要翻译： 具有堆叠结构的非易失性存储器件以及操作非易失性存储器件的方法其中非易失性存储器件包括布置在至少一层中的多个可变电阻器。 提供耦合到多个可变电阻器的至少一个层选择位线和多个位线。 耦合在多个位线和多个可变电阻之间的多个选择晶体管被设置。

公开(公告)号：US20070054445A1

公开(公告)日：2007-03-08

申请号：US11240473

申请日：2005-10-03

申请人： Hoon Kim ,  In-jae Song ,  Won-joo Kim ,  Byoung-lyong Choi

发明人： Hoon Kim ,  In-jae Song ,  Won-joo Kim ,  Byoung-lyong Choi

IPC分类号： H01L21/338 ,  H01L21/461

CPC分类号： H01L21/8238 ,  H01L21/3212 ,  H01L33/08 ,  H01L33/24 ,  Y10S977/755 ,  Y10S977/758 ,  Y10S977/773

摘要： Provided is a method of manufacturing a nano scale semiconductor device, such as a nano scale P-N junction device or a CMOS using nano particles without using a mask or a fine pattern. The method includes dispersing uniformly a plurality of nano particles on a semiconductor substrate, forming an insulating layer covering the nano particles on the semiconductor substrate, partly removing the upper surfaces of the nano particles and the insulating layer, selectively removing the nano particles from the insulating layer, and partly forming doped semiconductor layers in the semiconductor substrate by partly doping the semiconductor substrate through spaces formed by removing the nano particles.

摘要翻译： 提供了一种使用纳米级P-N结器件或使用纳米颗粒的CMOS而不使用掩模或精细图案的纳米级半导体器件的制造方法。 该方法包括在半导体衬底上均匀分散多个纳米颗粒，形成覆盖半导体衬底上的纳米颗粒的绝缘层，部分去除纳米颗粒和绝缘层的上表面，从绝缘体中选择性地除去纳米颗粒 层，并且通过部分地通过去除纳米颗粒形成的空间将半导体衬底部分地掺杂在半导体衬底中部分地形成掺杂半导体层。

公开(公告)号：US07348535B2

公开(公告)日：2008-03-25

申请号：US11354014

申请日：2006-02-15

申请人： Hyun-ku Jeong ,  Won-joo Kim ,  Young-chul Ko

发明人： Hyun-ku Jeong ,  Won-joo Kim ,  Young-chul Ko

IPC分类号： H01J40/14 ,  H01L21/30

CPC分类号： G02B26/0841

摘要： A metal line structure of an optical scanner and a method of fabricating the same are provided. The metal line structure of the optical scanner includes: a glass substrate having a metal line region etched to a predetermined depth; a metal line formed in the metal line region; a diffusion barrier layer that is formed on the glass substrate and covers the metal line; and an optical scanner structure combined with the glass substrate.

摘要翻译： 提供了一种光学扫描仪的金属线结构及其制造方法。 光学扫描器的金属线结构包括：具有蚀刻到预定深度的金属线区域的玻璃基板; 形成在金属线区域中的金属线; 扩散阻挡层，其形成在所述玻璃基板上并覆盖所述金属线; 以及与玻璃基板结合的光学扫描器结构。

公开(公告)号：US20090273054A1

公开(公告)日：2009-11-05

申请号：US12382106

申请日：2009-03-09

申请人： Suk-pil Kim ,  Won-joo Kim ,  Seung-hoon Lee

发明人： Suk-pil Kim ,  Won-joo Kim ,  Seung-hoon Lee

IPC分类号： H01L29/68

CPC分类号： H01L27/115 ,  H01L27/11206 ,  H01L27/24

摘要： A non-volatile memory device and methods of fabricating the device according to example embodiments involve a stacked layer structure. The non-volatile memory device may include at least one first horizontal electrode including a first sidewall and a second sidewall; at least one second horizontal electrode including a third sidewall and a fourth sidewall; wherein the third sidewall may be disposed to face the first sidewall; at least one vertical electrode may be interposed between the first sidewall and the third sidewall, in such a way as to cross or intersect each of the at least one first and second horizontal electrodes, and; at least one data storage layer that may be capable of locally storing a change of electrical resistance may be interposed where the at least one first horizontal electrode and the at least one vertical electrode cross or intersect and where the at least one horizontal electrode and the at least one vertical electrodes cross or intersect.

摘要翻译： 根据示例实施例的非易失性存储器件和制造器件的方法涉及堆叠层结构。 非易失性存储器件可以包括至少一个包括第一侧壁和第二侧壁的第一水平电极; 至少一个第二水平电极，包括第三侧壁和第四侧壁; 其中所述第三侧壁可以被设置为面对所述第一侧壁; 至少一个垂直电极可以插入在第一侧壁和第三侧壁之间，以便使得至少一个第一和第二水平电极中的每一个交叉或相交， 可以插入至少一个能够局部存储电阻变化的数据存储层，其中至少一个第一水平电极和至少一个垂直电极交叉或相交，并且其中至少一个水平电极和at 至少一个垂直电极交叉或相交。

公开(公告)号：US07192873B1

公开(公告)日：2007-03-20

申请号：US11240473

申请日：2005-10-03

申请人： Hoon Kim ,  In-jae Song ,  Won-joo Kim ,  Byoung-Iyong Choi

发明人： Hoon Kim ,  In-jae Song ,  Won-joo Kim ,  Byoung-Iyong Choi

IPC分类号： H01L21/311

CPC分类号： H01L21/8238 ,  H01L21/3212 ,  H01L33/08 ,  H01L33/24 ,  Y10S977/755 ,  Y10S977/758 ,  Y10S977/773

摘要： Provided is a method of manufacturing a nano scale semiconductor device, such as a nano scale P-N junction device or a CMOS using nano particles without using a mask or a fine pattern. The method includes dispersing uniformly a plurality of nano particles on a semiconductor substrate, forming an insulating layer covering the nano particles on the semiconductor substrate, partly removing the upper surfaces of the nano particles and the insulating layer, selectively removing the nano particles from the insulating layer, and partly forming doped semiconductor layers in the semiconductor substrate by partly doping the semiconductor substrate through spaces formed by removing the nano particles.

摘要翻译： 提供了一种使用纳米级P-N结器件或使用纳米颗粒的CMOS而不使用掩模或精细图案的纳米级半导体器件的制造方法。 该方法包括在半导体衬底上均匀分散多个纳米颗粒，形成覆盖半导体衬底上的纳米颗粒的绝缘层，部分去除纳米颗粒和绝缘层的上表面，从绝缘体中选择性地除去纳米颗粒 层，并且通过部分地通过去除纳米颗粒形成的空间将半导体衬底部分地掺杂在半导体衬底中部分地形成掺杂半导体层。

公开(公告)号：US5444026A

公开(公告)日：1995-08-22

申请号：US74761

申请日：1993-06-10

申请人： Chang-kyu Kim ,  Myeong-beom Lee ,  Ji-hyun Choi ,  Woo-in Joung ,  Young-jin Im ,  Won-joo Kim ,  Jin-gi Hong ,  Geung-won Kang

发明人： Chang-kyu Kim ,  Myeong-beom Lee ,  Ji-hyun Choi ,  Woo-in Joung ,  Young-jin Im ,  Won-joo Kim ,  Jin-gi Hong ,  Geung-won Kang

IPC分类号： H01L21/31 ,  H01L21/768 ,  H01L23/532 ,  H01L21/316

CPC分类号： H01L21/76838 ,  H01L21/76801 ,  H01L21/76828 ,  H01L21/76834 ,  H01L23/5329 ,  H01L2924/0002

摘要： The present invention forms a intermediate layer between a conductive layer and BPSG layer. In one embodiment, this intermediate layer is a buffer layer that absorbs excess P ions from the BPSG layer to suppress the formation of bubbles and thereby prevent short circuits that may be caused due to the presence of bubbles in the BPSG layer. In the second embodiment the intermediate layer is a thin nitride layer, which prevents the conductive layer and BPSG layer from being in direct contact with each other to suppress the formation of bubbles and also prevent short circuits that may be caused due to the presence of bubbles in the BPSG layer.

摘要翻译： 本发明在导电层和BPSG层之间形成中间层。 在一个实施方案中，该中间层是从BPSG层吸收多余P离子以抑制气泡形成并从而防止由于BPSG层中气泡的存在而引起的短路的缓冲层。 在第二实施例中，中间层是薄的氮化物层，其防止导电层和BPSG层彼此直接接触以抑制气泡的形成并且还防止由于气泡的存在而引起的短路 在BPSG层。

公开(公告)号：US09035309B2

公开(公告)日：2015-05-19

申请号：US12984972

申请日：2011-01-05

申请人： Young-soo Park ,  Won-joo Kim ,  Kyoo-chul Cho ,  Gi-jung Kim ,  Sam-jong Choi

发明人： Young-soo Park ,  Won-joo Kim ,  Kyoo-chul Cho ,  Gi-jung Kim ,  Sam-jong Choi

IPC分类号： H01L27/146

CPC分类号： H01L27/14629 ,  H01L27/14687

摘要： A three-dimensional (3D) CMOS image sensor (CIS) that sufficiently absorbs incident infrared-rays (IRs) and includes an infrared-ray (IR) receiving unit formed in a thin epitaxial film, thereby being easily manufactured using a conventional CIS process, a sensor system including the 3D CIS, and a method of manufacturing the 3D CIS, the 3D CIS including an IR receiving part absorbing IRs incident thereto by repetitive reflection to produce electron-hole pairs (EHPs); and an electrode part formed on the IR receiving part and collecting electrons produced by applying a predetermined voltage thereto.

摘要翻译： 一种三维（3D）CMOS图像传感器（CIS），其足以吸收入射的红外线（IR）并且包括形成在薄的外延膜中的红外线（IR）接收单元，由此容易地使用传统的CIS工艺 包括3D CIS的传感器系统和制造3D CIS的方法，3D CIS包括通过重复反射吸收入射到其中的IR的IR接收部分以产生电子 - 空穴对（EHP）; 以及形成在IR接收部上并且收集通过施加预定电压而产生的电子的电极部分。