公开(公告)号：US20080094875A1

公开(公告)日：2008-04-24

申请号：US11552464

申请日：2006-10-24

申请人： ChiaHua Ho ,  Erh-Kun Lai ,  Kuang Yeu Hsieh

发明人： ChiaHua Ho ,  Erh-Kun Lai ,  Kuang Yeu Hsieh

IPC分类号： G11C11/00

CPC分类号： G11C17/165 ,  B82Y10/00 ,  G11C11/5664 ,  G11C11/5678 ,  G11C11/5685 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0014 ,  G11C13/0016 ,  G11C13/0069 ,  G11C17/16 ,  G11C2213/31 ,  G11C2213/32 ,  G11C2213/77

摘要： A method is described for operating a bistable resistance random access memory having two memory layer stacks that are aligned in series is disclosed. The bistable resistance random access memory comprises two memory layer stacks per memory cell, the bistable resistance random access memory operates in four logic states, a logic “00” state, a logic “01” state, a logic “10” state and a logic “11” state. The relationship between the four different logic states can be represented mathematically by the two variables n and f and a resistance R. The logic “0” state is represented by a mathematical expression (1+f)R. The logic “1” state is represented by a mathematical expression (n+f)R. The logic “2” state is represented by a mathematical expression (1+nf)R. The logic “3” state is represented by a mathematical expression n(1+f)R.

摘要翻译： 描述了一种用于操作具有串联排列的两个存储层堆叠的双稳态电阻随机存取存储器的方法。 双稳态电阻随机存取存储器包括每个存储单元的两个存储层堆栈，双稳态电阻随机存取存储器以四个逻辑状态，逻辑“00”状态，逻辑“01”状态，逻辑“10”状态和逻辑 “11”状态。 四个不同逻辑状态之间的关系可以由两个变量n和f以及电阻R在数学上表示。逻辑“0”状态由数学表达式（1 + f）R表示。 逻辑“1”状态由数学表达式（n + f）R表示。 逻辑“2”状态由数学表达式（1 + nf）R表示。 逻辑“3”状态由数学表达式n（1 + f）R表示。

公开(公告)号：US20070158633A1

公开(公告)日：2007-07-12

申请号：US11463824

申请日：2006-08-10

申请人： Erh-Kun Lai ,  ChiaHua Ho ,  Kuang Yeu Hsieh

发明人： Erh-Kun Lai ,  ChiaHua Ho ,  Kuang Yeu Hsieh

IPC分类号： H01L47/00

CPC分类号： H01L45/06 ,  H01L45/1233 ,  H01L45/1293 ,  H01L45/144 ,  H01L45/1683

摘要： A non-volatile method with a self-aligned RRAM element. The method includes a lower electrode element, generally planar in form, having an inner contact surface. At the top of the device is a upper electrode element, spaced from the lower electrode element. A containment structure extends between the upper electrode element and the lower electrode element, and this element includes a sidewall spacer element having an inner surface defining a generally funnel-shaped central cavity, terminating at a terminal edge to define a central aperture; and a spandrel element positioned between the sidewall spacer element and the lower electrode, having an inner surface defining a thermal isolation cell, the spandrel inner walls being spaced radially outward from the sidewall spacer terminal edge, such that the sidewall spacer terminal edge projects radially inward from the spandrel element inner surface. ARRAM element extends between the lower electrode element and the upper electrode, occupying at least a portion of the sidewall spacer element central cavity and projecting from the sidewall spacer terminal edge toward and making contact with the lower electrode. In this manner, the spandrel element inner surface is spaced from the RRAM element to define a thermal isolation cell adjacent the RRAM element.

摘要翻译： 具有自对准RRAM元素的非易失性方法。 该方法包括具有内部接触表面的大体平面形状的下部电极元件。 在装置的顶部是与下部电极元件间隔开的上部电极元件。 容纳结构在上电极元件和下电极元件之间延伸，并且该元件包括侧壁间隔元件，其具有限定大致漏斗形中心腔的内表面，终止于端边缘以限定中心孔; 以及位于所述侧壁间隔元件和所述下电极之间的突出元件，具有限定了热隔离单元的内表面，所述凸起内壁与所述侧壁间隔件终端边缘径向向外间隔开，使得所述侧壁间隔件末端边缘径向向内突出 从弹簧元件内表面。 ARRAM元件在下电极元件和上电极之间延伸，占据侧壁间隔元件中心空腔的至少一部分并且从侧壁间隔件终端边缘朝向和与下电极接触。 以这种方式，伞形元件内表面与RRAM元件间隔开以限定与RRAM元件相邻的热隔离单元。

公开(公告)号：US07209390B2

公开(公告)日：2007-04-24

申请号：US10876378

申请日：2004-06-24

申请人： Hang-Ting Lue ,  Yen-Hao Shih ,  Kuang Yeu Hsieh ,  Ming-Hsiu Lee ,  Chao-I Wu ,  Tzu-Hsuan Hsu

发明人： Hang-Ting Lue ,  Yen-Hao Shih ,  Kuang Yeu Hsieh ,  Ming-Hsiu Lee ,  Chao-I Wu ,  Tzu-Hsuan Hsu

IPC分类号： G11C16/00

CPC分类号： G11C16/3481 ,  G11C16/0466 ,  G11C16/3436

摘要： A memory cell with a charge trapping structure is programmed using refill cycles that include a program pulse followed by a charge balancing pulse that causes ejection of electrons from the charge trapping structure. The refill cycle causes a blue spectrum shift in the charge trap distribution in the charge trapping structure. The algorithm includes program verify operations after the program pulse, and completes when a successful program verify operation occurs after a number of refill cycles. The charge retention properties can be greatly improved by these refill cycles.

摘要翻译： 具有电荷俘获结构的存储单元使用包括编程脉冲，随后是电荷平衡脉冲的再填充循环被编程，该电荷平衡脉冲引起电荷从电荷捕获结构的喷出。 充电周期引起电荷捕获结构中电荷陷阱分布的蓝色光谱偏移。 该算法包括在程序脉冲之后的程序验证操作，并且在多个填充循环之后发生成功的程序验证操作时完成。 通过这些再填充循环可以大大提高电荷保持性。

公开(公告)号：US07075828B2

公开(公告)日：2006-07-11

申请号：US10876377

申请日：2004-06-24

申请人： Hang-Ting Lue ,  Yen-Hao Shih ,  Kuang Yeu Hsieh

发明人： Hang-Ting Lue ,  Yen-Hao Shih ,  Kuang Yeu Hsieh

IPC分类号： G11C16/00

CPC分类号： G11C16/0475 ,  G11C16/0483 ,  G11C16/14 ,  G11C16/30

摘要： A method of operating a memory cell comprises applying a first procedure (typically erase) to establish a low threshold state including a first bias arrangement causing reduction in negative charge in the charge trapping structure, and a second bias arrangement tending to the induce balanced charge tunneling between the gate and the charge trapping structure and between the charge trapping structure in the channel. A second procedure (typically program) is used to establish a high threshold state in the memory cell, including a third bias arrangement that causes an increase in negative charge in the charge trapping structure.

摘要翻译： 一种操作存储器单元的方法包括施加第一过程（通常是擦除）以建立低阈值状态，包括引起电荷俘获结构中的负电荷减小的第一偏置装置，以及倾向于引起平衡电荷隧穿的第二偏置装置 在栅极和电荷捕获结构之间以及沟道中的电荷捕获结构之间。 第二程序（通常为程序）用于在存储器单元中建立高阈值状态，包括导致电荷俘获结构中的负电荷增加的第三偏置装置。

公开(公告)号：US20050237816A1

公开(公告)日：2005-10-27

申请号：US10876378

申请日：2004-06-24

申请人： Hang-Ting Lue ,  Yen-Hao Shih ,  Kuang Yeu Hsieh ,  Ming-Hsiu Lee ,  Chao-I Wu ,  Tzu-Hsuan Hsu

发明人： Hang-Ting Lue ,  Yen-Hao Shih ,  Kuang Yeu Hsieh ,  Ming-Hsiu Lee ,  Chao-I Wu ,  Tzu-Hsuan Hsu

IPC分类号： G11C11/36 ,  G11C16/04 ,  G11C16/34

CPC分类号： G11C16/3481 ,  G11C16/0466 ,  G11C16/3436

摘要： A memory cell with a charge trapping structure is programmed using refill cycles that include a program pulse followed by a charge balancing pulse that causes ejection of electrons from the charge trapping structure. The refill cycle causes a blue spectrum shift in the charge trap distribution in the charge trapping structure. The algorithm includes program verify operations after the program pulse, and completes when a successful program verify operation occurs after a number of refill cycles.

摘要翻译： 具有电荷俘获结构的存储单元使用包括编程脉冲，随后是电荷平衡脉冲的再填充循环被编程，该电荷平衡脉冲引起电荷从电荷捕获结构的喷出。 充电周期引起电荷捕获结构中电荷陷阱分布的蓝色光谱偏移。 该算法包括在程序脉冲之后的程序验证操作，并且在多个填充循环之后发生成功的程序验证操作时完成。

公开(公告)号：US20050237815A1

公开(公告)日：2005-10-27

申请号：US10876377

申请日：2004-06-24

申请人： Hang-Ting Lue ,  Yen-Hao Shih ,  Kuang Yeu Hsieh

发明人： Hang-Ting Lue ,  Yen-Hao Shih ,  Kuang Yeu Hsieh

IPC分类号： G11C16/02 ,  G11C16/04 ,  G11C16/14 ,  G11C16/30 ,  G11C16/34 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： G11C16/0475 ,  G11C16/0483 ,  G11C16/14 ,  G11C16/30

摘要： A method of operating a memory cell comprises applying a first procedure (typically erase) to establish a low threshold state including a first bias arrangement causing reduction in negative charge in the charge trapping structure, and a second bias arrangement tending to the induce balanced charge tunneling between the gate and the charge trapping structure and between the charge trapping structure in the channel. A second procedure (typically program) is used to establish a high threshold state in the memory cell, including a third bias arrangement that causes an increase in negative charge in the charge trapping structure.

摘要翻译： 一种操作存储器单元的方法包括施加第一过程（通常是擦除）以建立低阈值状态，包括引起电荷俘获结构中的负电荷减小的第一偏置装置，以及倾向于引起平衡电荷隧穿的第二偏置装置 在栅极和电荷捕获结构之间以及沟道中的电荷捕获结构之间。 第二程序（通常为程序）用于在存储器单元中建立高阈值状态，包括导致电荷俘获结构中的负电荷增加的第三偏置装置。

公开(公告)号：US07590005B2

公开(公告)日：2009-09-15

申请号：US11625236

申请日：2007-01-19

申请人： Tzu Hsuan Hsu ,  Chao-I Wu ,  Kuang Yeu Hsieh ,  Ya-Chin King

发明人： Tzu Hsuan Hsu ,  Chao-I Wu ,  Kuang Yeu Hsieh ,  Ya-Chin King

IPC分类号： G11C11/34

CPC分类号： G11C16/0466

摘要： The present invention describes a uniform program method and a uniform erase method of a charge trapping memory by employing a substrate transient hot electron technique for programming, and a substrate transient hot hole technique for erasing, which emulate an FN tunneling method for NAND memory operation. The methods of the present invention are applicable to a wide variety of charge trapping memories including n-channel or p-channel SONOS types of memories and floating gate (FG) type memories. The programming of the charge trapping memory is conducted using a substrate transient hot electron injection in which a body bias voltage Vb has a short pulse width and a gate bias voltage Vg has a pulse width that is sufficient to move electrons from a channel region to a charge trapping structure.

摘要翻译： 本发明通过采用用于编程的衬底瞬态热电子技术和用于擦除的衬底瞬时热孔技术来描述电荷捕获存储器的均匀编程方法和均匀擦除方法，其模拟用于NAND存储器操作的FN隧穿方法。 本发明的方法可应用于包括n沟道或p沟道SONOS类型的存储器和浮动栅（FG）型存储器的各种电荷捕获存储器。 电荷捕获存储器的编程是使用衬底瞬态热电子注入进行的，其中体偏置电压Vb具有短的脉冲宽度，并且栅极偏置电压Vg具有足以将电子从沟道区域移动到 电荷捕获结构。

公开(公告)号：US07200045B2

公开(公告)日：2007-04-03

申请号：US11026708

申请日：2004-12-30

申请人： Hang-Ting Lue ,  Kuang Yeu Hsieh

发明人： Hang-Ting Lue ,  Kuang Yeu Hsieh

IPC分类号： G11C11/34

CPC分类号： G11C16/12 ,  G11C16/0466

摘要： A raised-Vs Channel Initialed Secondary Electron Injection is disclosed to program a charge-trapping nonvolatile memory cell. The source of the charge-trapping nonvolatile memory cell is applied with a positive source voltage, and the drain of the charge-trapping nonvolatile memory cell is applied with a positive drain voltage, wherein the positive drain voltage is greater than the positive source voltage. The substrate of the charge-trapping nonvolatile memory cell is grounded. A positive gate voltage is applied to the polysilicon gate of the charge-trapping nonvolatile memory cell.

摘要翻译： 公开了一种凸起Vs通道初始二次电子注入来对电荷捕获非易失性存储单元进行编程。 电荷捕获非易失性存储单元的源极被施加正的源极电压，并且电荷俘获非易失性存储单元的漏极被施加正的漏极电压，其中正的漏极电压大于正的源极电压。 电荷捕获非易失性存储单元的衬底接地。 正栅极电压被施加到电荷捕获非易失性存储单元的多晶硅栅极。

公开(公告)号：US20110116317A1

公开(公告)日：2011-05-19

申请号：US12985743

申请日：2011-01-06

申请人： TZU HSUAN HSU ,  Chao-I Wu ,  Kuang Yeu Hsieh ,  Ya-Chin King

发明人： TZU HSUAN HSU ,  Chao-I Wu ,  Kuang Yeu Hsieh ,  Ya-Chin King

IPC分类号： G11C16/04

CPC分类号： G11C16/0466

摘要： The present invention describes a uniform program method and a uniform erase method of a charge trapping memory by employing a substrate transient hot electron technique for programming, and a substrate transient hot hole technique for erasing, which emulate an FN tunneling method for NAND memory operation. The methods of the present invention are applicable to a wide variety of charge trapping memories including n-channel or p-channel SONOS types of memories and floating gate (FG) type memories. the programming of the charge trapping memory is conducted using a substrate transient hot electron injection in which a body bias voltage Vb has a short pulse width and a gate bias voltage Vg has a pulse width that is sufficient to move electrons from a channel region to a charge trapping structure.

摘要翻译： 本发明通过采用用于编程的衬底瞬态热电子技术和用于擦除的衬底瞬时热孔技术来描述电荷俘获存储器的均匀编程方法和均匀擦除方法，其模拟用于NAND存储器操作的FN隧道法。 本发明的方法可应用于包括n沟道或p沟道SONOS类型的存储器和浮动栅（FG）型存储器的各种电荷捕获存储器。 使用衬底瞬态热电子注入进行电荷俘获存储器的编程，其中体偏置电压Vb具有短的脉冲宽度，并且栅极偏置电压Vg具有足以将电子从沟道区域移动到 电荷捕获结构。

公开(公告)号：US07881123B2

公开(公告)日：2011-02-01

申请号：US11234678

申请日：2005-09-23

申请人： Hang Ting Lue ,  Kuang Yeu Hsieh

发明人： Hang Ting Lue ,  Kuang Yeu Hsieh

IPC分类号： G11C16/04

CPC分类号： G11C16/0475 ,  G11C11/5671 ,  G11C16/12 ,  G11C2211/5641

摘要： Disclosed are various embodiments that program a memory array with different carrier movement processes. In one application, memory cells are programmed with a particular carrier movement process depending on the pattern of data usage, such as code flash and data flash. In another application, memory cells are programmed with a particular carrier movement process depending on particular threshold voltage state to be programmed, in a multi-level cell scheme.

摘要翻译： 公开了对具有不同载体移动过程的存储器阵列进行编程的各种实施例。 在一个应用中，根据数据使用的模式，例如代码闪存和数据闪存，存储器单元被编程为特定的载波移动过程。 在另一应用中，存储器单元以特定载波移动过程编程，取决于要编程的特定阈值电压状态，在多级单元方案中。