公开(公告)号：US20050048788A1

公开(公告)日：2005-03-03

申请号：US10649099

申请日：2003-08-26

Applicant: Woody Tang ,  George Kovall ,  Yi Ding

Inventor： Woody Tang ,  George Kovall ,  Yi Ding

IPC: H01L21/033 ,  H01L21/3213 ,  H01L21/302 ,  H01L21/461

CPC classification number: H01L21/0332 ,  H01L21/32136 ,  H01L21/32139

Abstract: Significant amounts of micromasking residue have been observed at the interface between a Ti-containing ARC layer and a PE-TEOS hardmask after the hardmask has been etched and prior to the use of the etched hardmask for transferring a pattern to an underlying metal layer (e.g., aluminum). The micromasking residue can interfere with proper etching of the underlying metal layer such as by creating undesirable short circuits between metal interconnect lines. Methods are disclosed for removing and/or preventing the formation of the micromasking residue. A removing method includes the use of a relatively low average-mass physical bombardment agent in combination with a small-diameter, chemically-reactive agent for dislodging micromasking nodules by weakening their base anchors and breaking them away without causing excessive damage to underlying layers. In one embodiment, the base anchors are rich in titanium content while the micromasking nodule bodies contain titanium oxide. Chlorine is included in a residue removing plasma for volatizing the titanium of the base anchors while argon is further included in the residue removing plasma for physically bombarding the upper, oxide bodies of the micromasking nodules. A method for preventing or reducing the amount of formed, micromasking residue includes interposing an oxygen-poor interfacial layer between the metal-containing ARC layer and the oxygen-containing hardmask.

Abstract translation: 在硬掩模被蚀刻之后并且在使用蚀刻的硬掩模以将图案转移到下面的金属层之前，在含Ti的ARC层和PE-TEOS硬掩模之间的界面处观察到显着量的微掩模残留物（例如 ，铝）。 微掩模残留物可能妨碍下面的金属层的适当蚀刻，例如通过在金属互连线之间产生不期望的短路。 公开了用于去除和/或防止形成微阵列残留物的方法。 除去方法包括使用相对较低的平均质量物理轰击剂与小直径的化学反应剂组合，以通过削弱其基本锚固件并将其破坏而不会对下面的层造成过度损伤来移除微拉伸结节。 在一个实施方案中，基础锚固体富含钛含量，而微组织结核体中含有氧化钛。 残留物除去等离子体中的氯，用于挥发基础锚的钛，同时氩还包括在除去等离子体的残留物中以物理地轰击微掩模结核的上部氧化物体。 防止或减少形成的微掩模残渣量的方法包括在含金属的ARC层和含氧硬掩模之间插入不透氧的界面层。

公开(公告)号：US20050026365A1

公开(公告)日：2005-02-03

申请号：US10631941

申请日：2003-07-30

Applicant: Yi Ding

Inventor： Yi Ding

IPC: G11C11/34 ,  G11C16/04 ,  H01L21/336 ,  H01L21/8247 ,  H01L27/105 ,  H01L27/115 ,  H01L29/423 ,  H01L29/76 ,  H01L29/788

CPC classification number: H01L27/11526 ,  G11C16/0458 ,  H01L21/28273 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11546 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/7883 ,  H01L29/7885 ,  H01L29/7887

Abstract: In a memory cell (110) having multiple floating gates (160), the select gate (140) is formed before the floating gates. In some embodiments, the memory cell also has control gates (170) formed after the select gate. Substrate isolation regions (220) are formed in a semiconductor substrate (120). The substrate isolation regions protrude above the substrate. Then select gate lines (140) are formed. Then a floating gate layer (160) is deposited. The floating gate layer is etched until the substrate isolation regions are exposed. A dielectric (164) is formed over the floating gate layer, and a control gate layer (170) is deposited. The control gate layer protrudes upward over each select gate line. These the control gates and the floating gates are defined independently of photolithographic alignment. In another aspect, a nonvolatile memory cell has at least two conductive floating gates (160). A dielectric layer (164) overlying the floating gate has a continuous feature that overlies the floating gate and also overlays a sidewall of the select gate (140). Each control gate (160) overlies the continuous feature of the dielectric layer and also overlies the floating gate. In another aspect, substrate isolation regions (220) are formed in a semiconductor substrate. Select gate lines cross over the substrate isolation regions. Each select gate line has a planar top surface, but its bottom surface goes up and down over the substrate isolation regions. Other features are also provided.

Abstract translation: 在具有多个浮动栅极（160）的存储单元（110）中，在浮置栅极之前形成选择栅极（140）。 在一些实施例中，存储器单元还具有在选择栅极之后形成的控制栅极（170）。 衬底隔离区（220）形成在半导体衬底（120）中。 衬底隔离区突出于衬底上方。 然后选择栅极线（140）。 然后沉积浮栅层（160）。 蚀刻浮栅，直到衬底隔离区露出。 在浮动栅极层上形成电介质（164），并沉积控制栅极层（170）。 控制栅极层在每个选择栅极线上向上突出。 这些控制栅极和浮置栅极独立于光刻对准来定义。 在另一方面，非易失性存储单元具有至少两个导电浮动栅极（160）。 覆盖浮动栅极的介电层（164）具有覆盖在浮动栅极上并且还覆盖选择栅极（140）的侧壁的连续特征。 每个控制栅极（160）覆盖在电介质层的连续特征上并且也覆盖在浮动栅极上。 在另一方面，衬底隔离区（220）形成在半导体衬底中。 选择栅极线跨越衬底隔离区。 每个选择栅线具有平坦的顶表面，但其底表面在衬底隔离区上方上下移动。 还提供其他功能。

公开(公告)号：US20050026364A1

公开(公告)日：2005-02-03

申请号：US10631452

申请日：2003-07-30

Applicant: Yi Ding

Inventor： Yi Ding

IPC: H01L21/336 ,  H01L21/8239 ,  H01L21/8247 ,  H01L27/105

CPC classification number: H01L27/105 ,  H01L27/11526 ,  H01L27/11534

Abstract: A memory cell (110) has a select gate (140) and at least two floating gates (160). A gate dielectric (150) for the floating gates (160) is formed by thermal oxidation simultaneously with as a dielectric on a surface of the select gate (140). The dielectric thickness on the select gate is controlled by the dopant concentration in the select gate. Other features are also provided.

Abstract translation: 存储单元（110）具有选择栅极（140）和至少两个浮置栅极（160）。 用于浮动栅极（160）的栅极电介质（150）通过热氧化同时作为选择栅极（140）的表面上的电介质形成。 选择栅极上的电介质厚度由选择栅极中的掺杂剂浓度控制。 还提供其他功能。

公开(公告)号：US20050023564A1

公开(公告)日：2005-02-03

申请号：US10632007

申请日：2003-07-30

Applicant: Yi Ding

Inventor： Yi Ding

IPC: G11C16/04 ,  H01L21/8247 ,  H01L27/105 ,  H01L29/788 ,  H01L29/792 ,  H01L27/10 ,  H01L29/76

CPC classification number: H01L27/11526 ,  G11C16/0458 ,  H01L27/105 ,  H01L27/11543 ,  H01L27/11546 ,  H01L29/7887 ,  H01L29/7923 ,  Y10S257/905 ,  Y10S257/909 ,  Y10S257/92

Abstract: In a nonvolatile memory array in which each cell (110) has two floating gates (160), for any two consecutive memory cells, one source/drain region (174) of one of the cells and one source/drain region of the other one of the cells are provided by a contiguous region of the appropriate conductivity type (e.g. N type) formed in a semiconductor substrate (120). Each such contiguous region provides source/drain regions to only two of the memory cells in that column. The bitlines (180) overlie the semiconductor substrate in which the source/drain regions are formed. The bitlines are connected to the source/drain regions.

Abstract translation: 在其中每个单元（110）具有两个浮动栅极（160）的非易失性存储器阵列中，对于任何两个连续的存储单元，一个单元的一个源极/漏极区域（174）和另一个单元的一个源极/漏极区域 的单元由形成在半导体衬底（120）中的适当导电类型（例如N型）的连续区域提供。 每个这样的连续区域仅向该列中的两个存储单元提供源极/漏极区域。 位线（180）覆盖其中形成源极/漏极区域的半导体衬底。 位线连接到源极/漏极区域。

公开(公告)号：US06805972B2

公开(公告)日：2004-10-19

申请号：US10386924

申请日：2003-03-13

Applicant: Jonah Erlebacher ,  Yi Ding

Inventor： Jonah Erlebacher ,  Yi Ding

IPC: G32B324

CPC classification number: B01D67/0044 ,  B01D67/0058 ,  B01D71/022 ,  B01D2323/08 ,  B22F3/1134 ,  Y10T428/12431 ,  Y10T428/12479

Abstract: The present invention is directed to nanoporous metal membranes and methods of making nanoporous metal membranes from metal leaf. At least a portion of the metal leaf is freely supported by a de-alloying medium for a time effective to de-alloy the metal leaf. After the porous membrane is formed, the membrane may be re-adhered to a substrate and removed from the de-alloying medium. The de-alloying process may be thermally and electrically influenced.

公开(公告)号：US06733909B2

公开(公告)日：2004-05-11

申请号：US09848397

申请日：2001-05-03

Applicant: Yi Ding ,  Joseph Carl Burba

Inventor： Yi Ding ,  Joseph Carl Burba

IPC: H01M818

CPC classification number: H01M8/04238 ,  H01M8/0662 ,  H01M8/0668

Abstract: The invention is an improved fuel cell system suited for application in a vehicle. Specifically, the invention provides an improved system to remove CO emissions that has a rapid dynamic response (about 1 second) and can operate over a wide range of temperatures (between 0 and 800 degrees Celsius). The fuel cell system comprises hydrogen fuel, a CO removal system based upon non-Faradaic electrochemical modification of catalyst activity (electrochemical promotion), and a fuel cell stack. The CO removal system comprises a catalyst/working electrode, an electrolyte, a counter electrode, and a power source. The CO removal system's intrinsic catalytic rate is greater than an intrinsic electrocatalytic rate. The catalyst can be Pt, Rh, Au, Cu/ZnO, Cu/CuO, ABO3(perovskite), zeolite, and Pd. The power source can be a battery, potentiostat, or galvanostat.

Abstract translation: 本发明是适用于车辆的改进的燃料电池系统。 具体地，本发明提供了一种改进的系统，用于去除具有快速动态响应（约1秒）并且可在宽的温度范围（0至800摄氏度）之间工作的CO排放。 燃料电池系统包括氢燃料，基于催化剂活性（电化学促进）的非法拉第电化学改性的CO去除系统和燃料电池堆。 CO去除系统包括催化剂/工作电极，电解质，对电极和电源。 CO去除系统的内在催化速率大于固有的电催化速率。 催化剂可以是Pt，Rh，Au，Cu / ZnO，Cu / CuO，ABO3（钙钛矿），沸石和Pd。 电源可以是电池，恒电位仪或恒电位仪。

公开(公告)号：US06449405B1

公开(公告)日：2002-09-10

申请号：US09676293

申请日：2000-09-28

Applicant: Mario J. Paniccia ,  Yi Ding ,  Dmitri E. Nikonov

Inventor： Mario J. Paniccia ,  Yi Ding ,  Dmitri E. Nikonov

IPC: G02B642

CPC classification number: G02F1/025 ,  G02B2006/12145

Abstract: A device for confining an optical beam in an optical switch. In one embodiment, the disclosed optical switch includes an optical switching device disposed between an optical input port and an optical output port in a semiconductor substrate layer disposed between a plurality of optical confinement layers such that an optical beam is confined to remain within the layers. In one embodiment, a plurality of semiconductor substrate layers are included in the optical switch. Each of the semiconductor substrate layers is disposed between optical confinement layers such that optical beams passing through the semiconductor substrate layers are confined to remain within the semiconductor substrate layers until exiting through respective optical output ports. In one embodiment, integrated circuitry such as driver circuitry, controller circuitry, logic circuitry, coder-decoder circuitry, microprocessor circuitry or the like is included in at least one of the semiconductor substrate layers.

Abstract translation: 用于将光束限制在光开关中的装置。 在一个实施例中，所公开的光开关包括设置在设置在多个光限制层之间的半导体衬底层中的光输入端口和光输出端口之间的光开关器件，使得光束被限制在残留在层内。 在一个实施例中，光开关中包括多个半导体衬底层。 每个半导体衬底层设置在光学限制层之间，使得通过半导体衬底层的光束被限制为保留在半导体衬底层内，直到通过相应的光学输出端口离开。 在一个实施例中，诸如驱动器电路，控制器电路，逻辑电路，编码器 - 解码器电路，微处理器电路等的集成电路被包括在至少一个半导体衬底层中。

公开(公告)号：US06351576B1

公开(公告)日：2002-02-26

申请号：US09471936

申请日：1999-12-23

Applicant: Yi Ding

Inventor： Yi Ding

IPC: G02B612

CPC classification number: G06F1/105 ,  G02B6/12004 ,  G02B6/43 ,  G02B2006/12107

Abstract: The invention relates to an optical clocking signal distribution article that comprises a substrate that has a front surface and a back surface that are parallel planar. A dielectric layer is disposed upon the front surface, and a recess in the substrate exposes a portion of the dielectric layer when viewed from the back surface. A first light reflecting structure is disposed in the dielectric layer. The first reflecting structure is disposed within the exposed portion of the dielectric layer. At least one light receiver is disposed upon the front surface. Also disclosed is a method of forming an optical distribution structure. The method comprises forming a recess through a substrate to expose a dielectric layer. The method further comprises forming a waveguide in the dielectric layer, wherein the waveguide has a length, a first end, and a second end, and wherein the recess is disposed over the first end of the waveguide. The method also comprises forming a first light reflecting structure at the first end of the waveguide.

Abstract translation: 本发明涉及一种光时钟信号分配制品，其包括具有平行平面的前表面和后表面的基片。 电介质层设置在前表面上，并且当从后表面观察时，基板中的凹部露出电介质层的一部分。 第一光反射结构设置在电介质层中。 第一反射结构设置在电介质层的暴露部分内。 至少一个光接收器设置在前表面上。 还公开了一种形成光分布结构的方法。 该方法包括通过衬底形成凹陷以暴露电介质层。 该方法还包括在电介质层中形成波导，其中波导具有长度，第一端和第二端，并且其中凹部设置在波导的第一端上方。 该方法还包括在波导的第一端形成第一光反射结构。

公开(公告)号：US6094033A

公开(公告)日：2000-07-25

申请号：US165944

申请日：1998-10-02

Applicant: Yi Ding ,  Robert Michelson ,  Charles Stancil

Inventor： Yi Ding ,  Robert Michelson ,  Charles Stancil

IPC: H01M10/44 ,  H02J7/00 ,  H01M7/44

CPC classification number: H02J7/0008 ,  H01M10/44 ,  H02J7/0093 ,  Y02B40/90

Abstract: A battery state of charge (SOC) detector for rapid charging and method each provide an efficient means for formatting, charging, and recharging batteries of various types and ratings. The detector determines the SOC of a battery to be charged and then selects an optimal charging signal profile based on the SOC determination. During the charging process, the detector can continuously monitor battery SOC in order to select appropriate waveforms for the charging signal. The charging signal is a pulse width and amplitude modulated current, voltage or power waveform with the amplitude and pulse width of each charging pulse being selected based upon the detected battery SOC. Predetermined battery parameters, such as equivalent circuit capacitance and resistance, electrochemical overcharge, maximum battery temperature, and maximum battery internal pressure, among others, also can be compared with monitored values during the battery charging process to control the charging signal in order to avoid battery damage. The charging process is continued until detected battery SOC reaches 100% or until charging logic indicates that the charging process should be stopped.

Abstract translation: 用于快速充电的电池充电状态（SOC）检测器和方法均为各种类型和等级的电池的格式化，充电和充电提供了有效的手段。 检测器确定要充电的电池的SOC，然后基于SOC确定选择最佳充电信号曲线。 在充电过程中，检测器可以连续监测电池SOC，以便为充电信号选择合适的波形。 充电信号是基于检测到的电池SOC选择每个充电脉冲的幅度和脉冲宽度的脉冲宽度和幅度调制电流，电压或功率波形。 还可以将预定电池参数，例如等效电路电容和电阻，电化学过充电，最大电池温度和最大电池内部压力等与电池充电过程中的监视值进行比较，以控制充电信号，以避免电池 损伤。 充电过程继续进行，直到检测到的电池SOC达到100％，或者直到充电逻辑指示充电过程应停止为止。

公开(公告)号：US11660980B2

公开(公告)日：2023-05-30

申请号：US14959805

申请日：2015-12-04

Applicant: Anna G. Stefanopoulou ,  Shankar Narayan Mohan ,  Youngki Kim ,  Jason B. Siegel ,  Yi Ding ,  Wesley G. Zanardelli ,  Sonya Zanardelli

Inventor： Anna G. Stefanopoulou ,  Shankar Narayan Mohan ,  Youngki Kim ,  Jason B. Siegel ,  Yi Ding ,  Wesley G. Zanardelli ,  Sonya Zanardelli

IPC: H02J7/00 ,  B60L58/27 ,  H01M10/615 ,  H01M10/44 ,  H01M10/0525 ,  H01M10/42 ,  H02J7/34

CPC classification number: B60L58/27 ,  H01M10/0525 ,  H01M10/425 ,  H01M10/44 ,  H01M10/615 ,  H02J7/0042 ,  H02J7/34 ,  H01M2220/20 ,  Y02E60/10 ,  Y02T10/70

Abstract: There is disclosed an electrical device and a method in which a battery is warmed up when operating from a sub-zero temperature. The electrical device may include a battery; an electrical storage element; and a battery management system including a controller in electrical communication with the battery and the electrical storage element. The controller can be configured to execute a program stored in the controller to shuttle energy between the battery and the electrical storage element until a power capability threshold of the battery has been reached, Shuttling the energy raises a temperature of the battery to meet power demand.