Systems and methods for controlling the voltage on the lens of electron emitter devices

    公开(公告)号:US07102979B2

    公开(公告)日:2006-09-05

    申请号:US10046443

    申请日:2001-11-07

    Applicant: J. Craig Raese

    Inventor: J. Craig Raese

    CPC classification number: B82Y10/00 G11B9/10 G11B9/14 G11B9/1409 G11B9/1445

    Abstract: Methods for controlling the voltage on a lens of an electron emitting device are provided. A representative method includes: supplying an emitter voltage to an electron emitter in the electron emitting device, wherein a current amplitude is established; sensing the emitter voltage on the electron emitter; supplying a non-inverted input voltage to an amplifier that follows the emitter voltage; and providing an amplifier output voltage from the amplifier to the lens, wherein the amplifier output voltage corresponds to the emitter voltage at the electron emitter. Systems, devices and other methods also are provided.

    Photosensor array using multiple exposures to reduce thermal noise
    82.
    发明授权
    Photosensor array using multiple exposures to reduce thermal noise 失效
    光电传感器阵列使用多次曝光降低热噪声

    公开(公告)号:US07102679B1

    公开(公告)日:2006-09-05

    申请号:US09558434

    申请日:2000-04-25

    CPC classification number: H04N5/3692 H04N5/361 H04N5/37213

    Abstract: In an image scanner, multiple exposures are used for each scan line, and only part of the pixels for each scan line are used for each exposure. For example, with two exposures, half the pixels may be used for the first exposure, and half for the second exposure. For each exposure, half of the charges are shifted out rapidly and discarded, without waiting for the A/D conversion time. As a result, for each exposure, the time required to empty the charge shift register is greatly reduced, reducing the thermal noise for all pixels.

    Abstract translation: 在图像扫描器中,对于每个扫描线使用多次曝光,并且对于每次曝光仅使用每条扫描线的部分像素。 例如,通过两次曝光,可以将一半像素用于第一曝光,一半用于第二次曝光。 对于每次曝光,一半的费用被快速地移出并被丢弃,而不用等待A / D转换时间。 结果,对于每次曝光,大大减少了清空电荷移位寄存器所需的时间,降低了所有像素的热噪声。

    Memory stack architecture for reduced TLB misses
    83.
    发明授权
    Memory stack architecture for reduced TLB misses 失效
    用于减少TLB未命中的内存栈架构

    公开(公告)号:US07100014B2

    公开(公告)日:2006-08-29

    申请号:US10662734

    申请日:2003-09-15

    Abstract: One embodiment disclosed relates to a computer system. The computer system includes a microprocessor, an operating system, and a memory system. The microprocessor includes a register stack and a register stack engine (RSE), and the operating system includes a kernel. The memory system is configured to have a single memory page that includes both a kernel stack and an RSE stack. The memory system may be further configured such that the kernel stack and the RSE stack grow in opposite directions and such that a uarea data structure is located between those two stacks.

    Abstract translation: 所公开的一个实施例涉及一种计算机系统。 计算机系统包括微处理器,操作系统和存储器系统。 微处理器包括寄存器堆栈和寄存器堆栈引擎(RSE),并且操作系统包括内核。 内存系统配置为具有包含内核堆栈和RSE堆栈的单个内存页面。 可以进一步配置存储器系统,使得内核堆栈和RSE堆栈以相反的方向生长,并且使得uarea数据结构位于这两个堆栈之间。

    Method and system for enhancing images using edge orientation

    公开(公告)号:US07088474B2

    公开(公告)日:2006-08-08

    申请号:US09953003

    申请日:2001-09-13

    Abstract: A method and system for enhancing images utilizes the direction of a detected edge within an image block of an input image to selectively smooth or sharpen a pixel of the input image that corresponds to that image block. The direction of a detected edge within the image block is determined by computing the horizontal gradient and the vertical gradient, and then using the ratio of the computed gradients. In an exemplary embodiment, the method and system is designed to exclusively use bit shifting to perform multiplications, rather than using digital signal processing. Consequently, the method and system is suitable for implementation in printer firmware and/or hardware.

    Designing interconnect fabrics
    88.
    发明授权
    Designing interconnect fabrics 失效
    设计互连面料

    公开(公告)号:US07000011B1

    公开(公告)日:2006-02-14

    申请号:US09707227

    申请日:2000-11-06

    Applicant: Julie Ann Ward

    Inventor: Julie Ann Ward

    CPC classification number: H04L49/10

    Abstract: A method for designing an interconnect fabric for communication between a set of source nodes and a set of terminal nodes. The method partitions the flow requirements of the interconnect fabric into flow-sets and merges the flow-sets to reduce insensibilities with respect to available ports on source and terminal nodes while taking into account costs and feasibility of implementation.

    Abstract translation: 一种用于设计用于一组源节点和一组终端节点之间的通信的互连结构的方法。 该方法将互连结构的流量需求分为流程集合,并将流程集合,以减少源节点和终端节点上可用端口的不敏感性,同时考虑到成本和可行性。

    Media stack tray status mechanism
    90.
    发明授权
    Media stack tray status mechanism 失效
    介质堆栈托盘状态机制

    公开(公告)号:US06986509B2

    公开(公告)日:2006-01-17

    申请号:US10773910

    申请日:2004-02-05

    Abstract: A mechanism for sensing the status of a media stack tray which dispenses media to a printing device, the media stack tray being associated with a dispensing device which dispenses media from the media stack tray. The mechanism includes a probe having at least two positions such that the probe is located in a first position when the media stack tray has an empty status and is located in a second position when the media stack tray has a loaded status. The probe is mounted relative to the media stack tray so that when the media stack tray has a loaded status the media is normally located between the probe and the dispensing device. The mechanism also includes a detector for detecting the position of the probe.

    Abstract translation: 一种用于感测将介质分配给打印装置的介质堆栈托盘的状态的机构,所述介质堆栈托盘与从所述介质堆栈托盘分配介质的分配装置相关联。 该机构包括具有至少两个位置的探针,使得当介质堆栈托盘具有空状态并且当介质堆栈托盘具有加载状态时位于第二位置时探针位于第一位置。 探针相对于介质堆栈托架安装,以便当介质堆栈托盘具有加载状态时,介质通常位于探头和分配装置之间。 该机构还包括用于检测探针的位置的检测器。

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