公开(公告)号：US06970457B1

公开(公告)日：2005-11-29

申请号：US09413644

申请日：1999-10-06

Applicant: Neil Richards ,  Gajinder Singh Panesar ,  John Carey ,  Peter Thompson

Inventor： Neil Richards ,  Gajinder Singh Panesar ,  John Carey ,  Peter Thompson

IPC: H04L12/54 ,  H04L12/70 ,  H04Q11/04 ,  H04Q11/06 ,  H04L15/56

CPC classification number: H04L12/5602 ,  H04L2012/5658 ,  H04L2012/5679 ,  H04Q11/0478

Abstract: A data reception unit for receiving a plurality of data streams over a data channel, the data streams being received as amounts of data and each amount of data comprising a data portion including data from a data stream and an identity portion identifying that data stream, the data reception unit comprising: a data stream memory comprising a plurality of data stream storage areas, each for storing data from a respective one of a set of the data streams, and an escape buffer; a first storage information memory for holding first storage information for facilitating storage in the respective data stream storage area of data from the set of the data streams; and a data storage controller for, for each received amount of data, receiving the identity portion of the amount of data and performing a storage operation comprising: accessing the first storage information memory; and if the first storage information memory holds first storage information for the data stream identified by the identity portion, storing the data portion of the amount of data in the data stream storage area corresponding to that data stream; and if the first storage information memory does not hold first storage information for the data stream identified by the identity portion, storing the data portion of the amount of data in the escape buffer; and a processing unit connected to the escape buffer for performing an assembly operation comprising executing steps to assemble the information stored in the escape buffer into respective data streams.

Abstract translation: 一种数据接收单元，用于通过数据信道接收多个数据流，所述数据流被接收为数据量，并且每个数据量包括包括来自数据流的数据和识别该数据流的标识部分的数据部分， 数据接收单元，包括：数据流存储器，包括多个数据流存储区域，每个数据流存储区域用于存储来自一组数据流中的相应一个的数据;以及逃生缓冲器; 第一存储信息存储器，用于保存用于便于在数据流的集合中存储数据的相应数据流存储区域中的第一存储信息; 以及数据存储控制器，用于针对每个接收的数据量，接收所述数据量的身份部分并执行存储操作，包括：访问所述第一存储信息存储器; 并且如果所述第一存储信息存储器保存由所述身份部分识别的数据流的第一存储信息，则将所述数据量的数据部分存储在与所述数据流对应的数据流存储区域中; 并且如果所述第一存储信息存储器不存储由所述身份部分识别的数据流的第一存储信息，则将所述数据量的数据部分存储在所述转义缓冲器中; 以及处理单元，连接到逃逸缓冲器，用于执行组装操作，包括执行将存储在逃逸缓冲器中的信息组装成相应数据流的步骤。

公开(公告)号：US20050243065A1

公开(公告)日：2005-11-03

申请号：US11119155

申请日：2005-04-29

Applicant: Jeff Raynor

Inventor： Jeff Raynor

IPC: G06F1/32 ,  G06F3/023 ,  G06F3/033 ,  G06F3/0354 ,  G06K9/22 ,  G09G5/08

CPC classification number: G06F3/03543

Abstract: A computer navigation device includes a movement sensor and a trigger device activated by a timer. The computer navigation device periodically transmits to a host computer a pre-defined signal corresponding with the signal that would otherwise be generated by the movement sensor on detection of specific movements of the computer navigation device.

Abstract translation: 计算机导航装置包括由定时器激活的运动传感器和触发装置。 计算机导航装置在检测到计算机导航装置的特定移动时，周期性地向主机计​​算机发送对应于否则将由移动传感器生成的信号的预定义信号。

公开(公告)号：US20050216802A1

公开(公告)日：2005-09-29

申请号：US11015772

申请日：2004-12-17

Applicant: Robert Warren

Inventor： Robert Warren

IPC: G01R31/3185 ,  G01R31/28

CPC classification number: G01R31/318563 ,  G01R31/318536

Abstract: An integrated circuit comprising (i) a plurality of portions, each portion including test control circuitry; and (ii) at least one test input arranged to receive test signals, the circuit having a test mode in which one or more of the plurality of portions are testable, wherein the circuit has a reset mode which has priority over the test mode.

Abstract translation: 一种集成电路，包括（i）多个部分，每个部分包括测试控制电路; 以及（ii）布置成接收测试信号的至少一个测试输入，所述电路具有其中所述多个部分中的一个或多个部分是可测试的测试模式，其中所述电路具有优于所述测试模式的重置模式。

公开(公告)号：US06912494B1

公开(公告)日：2005-06-28

申请号：US09692292

申请日：2000-10-19

Applicant: Peter Ballam

Inventor： Peter Ballam

IPC: G06F17/50 ,  G06G7/62

CPC classification number: G06F17/5036

Abstract: A method is described for reducing delays in an analogue simulation model of a hardware circuit. The method includes the steps of stimulating via an input an output of said analog model, said output and said input having a relatively high resistance therebetween and applying a pulse to a relatively low resistance, whereby when said pulse is applied to the relatively low resistance, the input is connected to said output via the relatively low resistance so that the time constant of the circuit is reduced.

Abstract translation: 描述了一种用于减少硬件电路的模拟仿真模型中的延迟的方法。 该方法包括以下步骤：通过输入激励所述模拟模型的输出，所述输出和所述输入之间具有相对高的电阻，并将脉冲施加到相对较低的电阻，由此当所述脉冲施加到相对较低的电阻时， 输入端通过相对较低的电阻连接到所述输出端，从而减小了电路的时间常数。

公开(公告)号：US06904398B1

公开(公告)日：2005-06-07

申请号：US09340776

申请日：1999-06-28

Applicant: Gajinder Singh Panesar

Inventor： Gajinder Singh Panesar

IPC: G06F17/50 ,  G06F9/455

CPC classification number: G06F17/5022 ,  G06F17/5045 ,  G06F2217/68

Abstract: A computer system for simulating an ASP comprises first processor means including execution means for simulating a functional model in a high level language and output means for outputting the state of the functional model at the end of a predetermined simulation phase, means for converting the functional model, including its state at the end of the predetermined simulation phase, into a simulation language for simulating the ASP at circuit level, and second processor means arranged to execute the simulation language to simulate the ASP at circuit level for a subsequent simulation phase.

Abstract translation: 一种用于模拟ASP的计算机系统包括第一处理器装置，包括用于模拟高级语言的功能模型的执行装置和用于在预定模拟阶段结束时输出功能模型的状态的输出装置，用于将功能模型 （包括其在预定模拟阶段结束时的状态）转换成用于在电路级模拟ASP的仿真语言，以及第二处理器装置，被配置为执行模拟语言以在后续仿真阶段的电路级模拟ASP。

公开(公告)号：US06891443B2

公开(公告)日：2005-05-10

申请号：US09944637

申请日：2001-08-31

Applicant: Tahir Rashid

Inventor： Tahir Rashid

IPC: H03K3/011 ,  H03K3/0231 ,  H03K3/26

CPC classification number: H03K3/011 ,  H03K3/0231

Abstract: An oscillator circuit is described comprising of a capacitor; a capacitor charging means arranged to supply a current to charge the capacitor to a first predetermined threshold voltage; a capacitor discharging means arranged to discharge the capacitor to a second predetermined threshold voltage; and a switching means arranged to switch between a capacitor discharging mode and a capacitor charging mode. The switching means is responsive to the capacitor reaching at least one of said threshold voltages. Furthermore at least one threshold voltage is determined by a threshold setting means, which provides a voltage threshold that varies to compensate for changes in temperature.

Abstract translation: 描述了包括电容器的振荡器电路; 电容器充电装置，被布置成提供电流以将电容器充电到第一预定阈值电压; 电容器放电装置，其布置成将电容器放电到第二预定阈值电压; 以及设置成在电容器放电模式和电容器充电模式之间切换的开关装置。 开关装置响应于电容器达到至少一个所述阈值电压。 此外，阈值设定装置确定至少一个阈值电压，阈值设定装置提供改变以补偿温度变化的电压阈值。

公开(公告)号：US06879213B2

公开(公告)日：2005-04-12

申请号：US10413499

申请日：2003-04-11

Applicant: Saul Darzy

Inventor： Saul Darzy

IPC: H03F3/30 ,  H03F3/26

CPC classification number: H03F3/3067

Abstract: A circuit is used in the output stage of an operational amplifier which allows a rail to rail swing of the output voltage while consuming low quiescent power. The circuit includes first and second control elements each having a controllable path and a control node. The circuit further includes a third control element having a controllable path connected between the control nodes of the first and second control elements via a resistive path. A voltage indicative of an input signal is applied to a node of the resistive path. Current flow through the controllable paths of the first and second control elements changes in response to changes in the voltage at the node. More specifically, current flow through the controllable path of the second control element changes in dependance on the current flow through the controllable path of the third control element. Additionally, as one of the first and second control elements is turned on, the other control element is held off.

Abstract translation: 在运算放大器的输出级使用电路，其允许轨道在输出电压的同时摆动，同时消耗低静态功率。 电路包括第一和第二控制元件，每个具有可控路径和控制节点。 电路还包括具有经由电阻路径连接在第一和第二控制元件的控制节点之间的可控路径的第三控制元件。 将表示输入信号的电压施加到电阻路径的节点。 通过第一和第二控制元件的可控路径的电流响应于节点处电压的变化而改变。 更具体地，通过第二控制元件的可控路径的电流依赖于通过第三控制元件的可控路径的电流流动。 此外，当第一和第二控制元件中的一个被接通时，另一个控制元件被关闭。

公开(公告)号：US20050076127A1

公开(公告)日：2005-04-07

申请号：US10913793

申请日：2004-08-06

Applicant: Julian Wilson ,  Steven Haydock ,  Brendan O'Connor

Inventor： Julian Wilson ,  Steven Haydock ,  Brendan O'Connor

IPC: H04N7/173 ,  H04L29/08 ,  G06F9/00

CPC classification number: H04L67/16 ,  H04L67/02 ,  H04L67/10 ,  H04L67/12 ,  H04L69/329

Abstract: A method and apparatus are provided for controlling services provided at a first electronic device at a second electronic device. A plurality of electronic devices connected to a network provide services in the form of providing data to the network, or allowing the data to be manipulated. Each service is represented as a manipulable data object created at the device providing the service. Each object contains sufficient information to allow the service the object represents to be controlled. The objects are transmitted over the network and are stored in an object list maintained by a master device. Any compatible device may then retrieve an object from the object list and use the information contained in it to fully control the service.

Abstract translation: 提供了一种用于控制在第二电子设备处提供在第一电子设备处的服务的方法和装置。 连接到网络的多个电子设备以向网络提供数据或者允许数据被操纵的形式提供服务。 每个服务都表示为在提供服务的设备上创建的可操纵的数据对象。 每个对象包含足够的信息来允许对象表示的服务被控制。 对象通过网络传输并存储在由主设备维护的对象列表中。 任何兼容设备然后可以从对象列表中检索对象，并使用其中包含的信息来完全控制服务。

公开(公告)号：US06864712B2

公开(公告)日：2005-03-08

申请号：US10426248

申请日：2003-04-28

Applicant: Deepak Agarwal ,  Parvesh Swami

Inventor： Deepak Agarwal ,  Parvesh Swami

IPC: G11C11/412 ,  H03K19/177

CPC classification number: G11C11/4125 ,  H03K19/17704 ,  H03K19/17764

Abstract: The present invention is concerned with a method and apparatus for hardening logic devices. The logic device has a plurality of memory cells forming an array connected by data lines and clock lines, and the device having a further connecting line. The method comprising: receiving data on said data lines for configuring each of the memory cells. Storing data in each of the memory cells by enabling at least one of the clock lines and when the desired data has been stored, hardening the array to fix the data by selectively connecting the data and clock lines to the further line.

Abstract translation: 本发明涉及用于硬化逻辑器件的方法和装置。 逻辑装置具有形成由数据线和时钟线连接的阵列的多个存储单元，并且该装置具有另外的连接线。 该方法包括：在所述数据线上接收用于配置每个存储单元的数据。 通过启用至少一个时钟线并且当期望的数据已经被存储时，通过使数据和时钟线选择性地连接到另一行，来硬化阵列以固定数据，将数据存储在每个存储器单元中。

公开(公告)号：US06856357B1

公开(公告)日：2005-02-15

申请号：US09591886

申请日：2000-06-09

Applicant: David Hugh Stevenson

Inventor： David Hugh Stevenson

IPC: H04N5/225

CPC classification number: H01L27/14618 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An image sensor device includes an image sensor chip and an image sensor array formed on a top surface of the image sensor chip. The image sensor chip is mounted on a substrate and encapsulated by a dam wall formed on the substrate surrounding the periphery of the image sensor chip and a transparent lid member affixed to the upper edges of the dam wall. A barrier is formed on the surface of the chip extending along at least a substantial part of at least one side of the sensor array between the sensor array and the dam wall. The barrier is preferably formed with a height of at least three microns and surrounds the sensor array. The barrier may be formed during fabrication of the sensor chip. Where the sensor chip is a color image sensor including a mosaic of color filter material overlying the image sensor array, the barrier may be formed from the color filter material with the formation of the mosaic. The barrier prevents resin bleeding from the dam wall onto the surface of the sensor array.

Abstract translation: 图像传感器装置包括图像传感器芯片和形成在图像传感器芯片的顶表面上的图像传感器阵列。 图像传感器芯片安装在基板上，并且由围绕图像传感器芯片的周边的基板上形成的阻挡壁封住，并且固定在坝壁的上边缘的透明盖构件。 在芯片的表面上形成有阻挡层，其沿传感器阵列的至少一侧的至少一部分的至少一部分在传感器阵列和坝壁之间延伸。 屏障优选地形成有至少三微米的高度并且围绕传感器阵列。 阻挡层可以在制造传感器芯片期间形成。 在传感器芯片是包括覆盖在图像传感器阵列上的彩色滤光片的马赛克的彩色图像传感器的情况下，可以通过形成马赛克的滤色器材料形成屏障。 屏障防止树脂从坝壁渗出到传感器阵列的表面上。