公开(公告)号：US08514889B2

公开(公告)日：2013-08-20

申请号：US13219496

申请日：2011-08-26

申请人： Doddaballapur N. Jayasimha ,  Jeremy Chan ,  Jay S. Tomlinson

发明人： Doddaballapur N. Jayasimha ,  Jeremy Chan ,  Jay S. Tomlinson

IPC分类号： H04J3/24 ,  H04L12/56

CPC分类号： H04L45/60

摘要： A method for routing information in a flexible routing network which connects disparate initiators and targets includes implementing a packetization logic at an interface between an initiator or a target and a routing network to receive transmission traffic from the initiator or the target and to packetize the transmission traffic into packets. Each packet includes header and body portions. Each of the header and body portions includes one or more standard sized transmission units. Each standard sized transmission unit includes control and payload sections. A payload section associated with the body portion includes one or more chunks. The method includes encoding the one or more chunks using a Common Data Format (CDF). All transmissions within the routing network are based on the CDF. The CDF facilitates narrow-to-wide and wide-to-narrow link width conversion without having to manipulate subparts of data fields in the transmission traffic.

摘要翻译： 用于在连接不同发起者和目标的灵活路由网络中路由信息的方法包括在发起者或目标与路由网络之间的接口处实现分组化逻辑，以接收来自发起者或目标的传输业务，并将传输业务 分组 每个包包括头部和主体部分。 头部和主体部分中的每一个包括一个或多个标准尺寸的传动单元。 每个标准尺寸的传输单元包括控制和有效载荷部分。 与主体部分相关联的有效载荷部分包括一个或多个块。 该方法包括使用公共数据格式（CDF）对一个或多个块进行编码。 路由网络内的所有传输均基于CDF。 CDF有助于窄到宽和宽到窄的链路宽度转换，而不必操纵传输业务中的数据字段的子部分。

公开(公告)号：US20130073878A1

公开(公告)日：2013-03-21

申请号：US13434605

申请日：2012-03-29

申请人： Doddaballapur N. Jayasimha ,  Drew E. Wingard ,  Stephen W. Hamilton

发明人： Doddaballapur N. Jayasimha ,  Drew E. Wingard ,  Stephen W. Hamilton

IPC分类号： G06F1/26

CPC分类号： G06F1/3287 ,  Y02D10/171 ,  Y02D50/20

摘要： An interconnect-power-manager (IPM) cooperates and communicates signals with an integrated-circuit-system-power-manager (SPM) in the integrated-circuit. The interconnect network (IN) is partitioned into multiple power domains and has hardware circuitry integrated into the IN to manage a quiescent state for all components in each power domain in the IN when a routing pathway for transactions in the IN spans across one or more power domain boundaries and causes interdependencies of power domains within the IN other than where the power domains of the initiator agent and final target agent of the transaction are located within. The SPM is configured to cooperate and communicate with the IPM to quiesce, to wake up, and any combination of the two, one or more of the multiple power domains within the IN.

摘要翻译： 互连功率管理器（IPM）与集成电路中的集成电路系统功率管理器（SPM）协作并传送信号。 互连网络（IN）被划分成多个电力域，并且当IN中的事务的路由路径跨越一个或多个电力时，将集成到IN中的硬件电路集成到IN中的每个电力域中的所有组件的静态状态 域内的边界，并导致IN内的电源域的相互依赖关系，而不是发起方代理的权力域和交易的最终目标代理所在的地方。 SPM被配置为与IPM协作和通信以静默，唤醒以及IN内的多个电力域中的两个，一个或多个的任何组合。

公开(公告)号：US20130051397A1

公开(公告)日：2013-02-28

申请号：US13219339

申请日：2011-08-26

申请人： LIPING GUO ,  DODDABALLAPUR N. JAYASIMHA ,  JEREMY CHAN

发明人： LIPING GUO ,  DODDABALLAPUR N. JAYASIMHA ,  JEREMY CHAN

IPC分类号： H04L12/28

CPC分类号： H04L49/253 ,  H04L45/00 ,  H04L45/586

摘要： A method includes receiving flits forwarded from an upstream router into a first input virtual channel (VC) associated with an input port. The flits are associated with packets originated from a first Intellectual Property (IP) core and forwarded to a second IP core. The flits are stored in a VC storage associated with the first input VC. The method further includes performing link width conversion based on a width of the flits being different from a width of an output port. Link width conversion includes accumulation of the flits when the width of the output port is wider and unpacking of the flits when the width of the output port is narrower. Credits are generated based on the flits being forwarded from the first input VC to the output port. The credits are sent to the upstream router to enable receiving more flits from the upstream router.

摘要翻译： 一种方法包括接收从上游路由器转发到与输入端口相关联的第一输入虚拟通道（VC）中的闪烁。 闪存与源自第一知识产权（IP）核心的数据包相关联，并转发到第二个IP内核。 闪存存储在与第一输入VC相关联的VC存储器中。 该方法还包括基于与输出端口的宽度不同的flits的宽度来执行链路宽度转换。 链路宽度转换包括当输出端口的宽度较宽时，当输出端口的宽度较窄时，flit的累积，以及flits的解包。 基于从第一输入VC转发到输出端口的闪烁生成积分。 信用被发送到上游路由器，以便能够从上游路由器接收更多的信元。

公开(公告)号：US08190804B1

公开(公告)日：2012-05-29

申请号：US12402707

申请日：2009-03-12

申请人： Krishnan Srinivasan ,  Drew E. Wingard

发明人： Krishnan Srinivasan ,  Drew E. Wingard

IPC分类号： G06F12/00 ,  G06F13/00

CPC分类号： G06F13/1615

摘要： Various methods and apparatus are described for a memory scheduler. The memory scheduler has a pipelined arbiter to determine which request will access the target memory core. Pipelining occurs in stages within the arbiter over a period of more than one clock cycle. The pipelined arbiter uses two or more weighting factors affecting an arbitration decision that are processed in parallel. A predictive scheduler in the memory scheduler uses data from a previous cycle to make the arbitration decision about a request during a current clock cycle in which the arbitration decision is made in order to increase overall system efficiency of requests being serviced in the integrated circuit.

摘要翻译： 描述了用于存储器调度器的各种方法和装置。 存储器调度器具有流水线仲裁器，以确定哪个请求将访问目标存储器核心。 流水线在多于一个时钟周期的时间内在仲裁器内分阶段发生。 流水线仲裁器使用两个或更多个加权因素影响并行处理的仲裁决策。 存储器调度器中的预测调度器使用来自前一周期的数据在当前时钟周期内作出关于请求的仲裁决定，其中作出仲裁决定以提高在集成电路中服务的请求的整体系统效率。

公开(公告)号：US20120110106A1

公开(公告)日：2012-05-03

申请号：US12938120

申请日：2010-11-02

申请人： BENOIT DE LESCURE ,  KRISHNAN SRINIVASAN

发明人： BENOIT DE LESCURE ,  KRISHNAN SRINIVASAN

IPC分类号： G06F15/16

CPC分类号： G06F15/16 ,  G06F13/4027 ,  G06F15/7825

摘要： A method, apparatus, and system for providing layer concurrency connecting two or more master Intellectual Property cores to a Network on a Chip (NoC) for an integrated circuit is provided. An embodiment includes two masters connected using a common tightly coupled protocol to a first interface of an NoC. A protocol conversion unit can be coupled between the two or more masters and the NoC to convert a request in the tightly coupled protocol to a decoupled protocol that decouples request phasing from response phasing and then passes the request in the decoupled protocol format onto the NoC. The system also provides for arbitration amongst the two or more masters. Requests from the masters are still in the common tightly coupled protocol and are translated by the protocol conversion unit into a request in a decoupled protocol to enable out of order return of responses.

摘要翻译： 提供了一种用于提供将两个或多个主要知识产权核心连接到用于集成电路的芯片上的网络（NoC）的层并发的方法，装置和系统。 一个实施例包括使用公共紧密耦合协议连接到NoC的第一接口的两个主机。 协议转换单元可以耦合在两个或更多个主设备和NoC之间，以将紧密耦合的协议中的请求转换为将请求定相与响应定相分离的去耦协议，然后将解耦协议格式的请求传递到NoC。 该系统还规定了两个或多个主人之间的仲裁。 来自主人的请求仍然处于通用的紧密耦合协议中，并由协议转换单元转换为解耦协议中的请求，以使响应无序返回。

公开(公告)号：US20110278218A1

公开(公告)日：2011-11-17

申请号：US13085299

申请日：2011-04-12

申请人： Jason Dionne ,  Bart Lipkens ,  Edward A. Rietman

发明人： Jason Dionne ,  Bart Lipkens ,  Edward A. Rietman

IPC分类号： B01D17/04

CPC分类号： C02F1/36 ,  B01D17/04 ,  B01D17/044 ,  B01D21/28 ,  C02F1/40 ,  C02F2101/325 ,  C02F2103/008 ,  C02F2103/10 ,  C02F2303/04

摘要： Several prototype systems are described for separating oil and water from emulsions. The systems operate at ultrasonic resonance and are thus low power. Each system contains one or more acoustic transducers operating in the 100 kHz to 5 MHz range. Each system contains flow input for the emulsion and two or more flow outputs for the separated oil and water. Existing prototypes operate from 200 mL/min to >15 L/min. Each uses low power in the range of 1-5 W.

摘要翻译： 描述了几种用于从乳液中分离油和水的原型系统。 这些系统以超声共振工作，因此功率低。 每个系统包含一个或多个在100 kHz至5 MHz范围内工作的声学换能器。 每个系统包含用于乳液的流量输入和用于分离的油和水的两个或多个流量输出。 现有原型从200 mL / min至> 15 L / min运行。 每个使用1-5W范围内的低功率。

公开(公告)号：US08032676B2

公开(公告)日：2011-10-04

申请号：US10980505

申请日：2004-11-02

申请人： Drew E. Wingard ,  Glenn S. Vinogradov

发明人： Drew E. Wingard ,  Glenn S. Vinogradov

IPC分类号： G06F3/00 ,  G06F13/00 ,  G06F13/40 ,  G06F11/00

CPC分类号： H04L49/3054 ,  H04L49/109

摘要： Embodiments of apparatuses, systems, and methods are described for communicating information between functional blocks of a system across a communication fabric. Rate logic may couple to the communication fabric. The rate logic is configured to determine a data bandwidth difference between a first data bandwidth capability of the sending device and the lower of 1) a second data bandwidth capability of the sending device or 2) a third data bandwidth capability of the communication fabric.

摘要翻译： 描述了用于在通信结构上的系统的功能块之间传送信息的装置，系统和方法的实施例。 速率逻辑可以耦合到通信结构。 速率逻辑被配置为确定发送设备的第一数据带宽能力与发送设备的第二数据带宽能力之间的数据带宽差异，或2）通信结构的第三数据带宽能力。

公开(公告)号：US08020124B2

公开(公告)日：2011-09-13

申请号：US12122988

申请日：2008-05-19

申请人： Herve Alexanian ,  Chien-Chun Chou ,  Vida Vakilotojar ,  Grigor Yeghiazaryan

发明人： Herve Alexanian ,  Chien-Chun Chou ,  Vida Vakilotojar ,  Grigor Yeghiazaryan

IPC分类号： G06F17/50

CPC分类号： G06F17/504 ,  G01R31/318314

摘要： Various methods and apparatuses are described for generating a model of hardware components making up an interconnect that facilitates communications between Intellectual Property blocks in an integrated circuit coded in a software programming language at a high level of abstraction that is cycle accurate to a corresponding lower level of abstraction description of the hardware components making up the interconnect. The sub-components of the model at the high level of abstraction are tested in a simulation environment in parallel with the same sub-components of a model coded in a hardware description language at the low level of abstraction in order to verify the functional accuracy and cycle timing between the two models. After the sub-components are tested, the sub-components of the model at the high level of abstraction may be aggregated into a single model at the high level of abstraction that is functionally accurate and cycle accurate to the model at the low level of abstraction.

摘要翻译： 描述了用于生成构成互连的硬件组件的模型的各种方法和装置，其有助于在以高抽象级别编码的集成电路中的知识产权块之间的通信，所述集成电路是循环准确地到相应的较低级别 构成互连的硬件组件的抽象描述。 在高抽象级别的模型的子组件在模拟环境中与在低抽象级别的硬件描述语言中编码的模型的相同子组件并行进行测试，以验证功能精度和 两个模型之间的循环时序。 在子组件被测试之后，在高抽象级别的模型的子组件可以在抽象的高水平聚合成单个模型，其功能准确并且在低抽象级别对模型进行周期准确 。

公开(公告)号：US20100318946A1

公开(公告)日：2010-12-16

申请号：US12729509

申请日：2010-03-23

申请人： Stephen Hamilton ,  Ian Andrew Swarbrick ,  Scott Carlton Evans ,  Wolf-Dietrich Weber ,  Jay S. Tomlinson

发明人： Stephen Hamilton ,  Ian Andrew Swarbrick ,  Scott Carlton Evans ,  Wolf-Dietrich Weber ,  Jay S. Tomlinson

IPC分类号： G06F17/50

CPC分类号： G06F17/5045 ,  G06F17/50 ,  G06F2217/78 ,  G06F2217/84

摘要： Methods and apparatuses are described for an Intellectual Property (IP) Generator for estimating timing, area, and power characteristics of an electronic system design. The IP Generator receives a user-supplied file having data describing a configuration of an IP design having multiple levels of hierarchy. The IP Generator also receives user-supplied technology parameters and data-flow information. The IP generator correlates estimated timing, area, and power characteristics for each IP sub component based on the user supplied technology parameters, data-flow information and configuration parameters. The IP generator reports the timing, area, and power estimates to a user via a graphic user interface prior to a transformation of a Register Transfer Level (RTL) design into the gate-level circuit design.

摘要翻译： 描述了用于估计电子系统设计的时间，面积和功率特性的知识产权（IP）发生器的方法和装置。 IP生成器接收用户提供的文件，该文件具有描述具有多层次结构的IP设计的配置的数据。 IP生成器还接收用户提供的技术参数和数据流信息。 IP生成器根据用户提供的技术参数，数据流信息和配置参数，关联每个IP子组件的估计时序，面积和功率特性。 在将寄存器传输级别（RTL）设计转换为门级电路设计之前，IP生成器通过图形用户界面向用户报告定时，面积和功率估计。

公开(公告)号：US07660932B2

公开(公告)日：2010-02-09

申请号：US12022912

申请日：2008-01-30

申请人： Chien Chun Chou ,  Wolf-Dietrich Weber ,  Drew E. Wingard

发明人： Chien Chun Chou ,  Wolf-Dietrich Weber ,  Drew E. Wingard

IPC分类号： G06F13/00

CPC分类号： H04L69/18 ,  G06F15/7825

摘要： Embodiments of apparatuses, systems, and methods are described for a machine-readable medium having instructions stored thereon, which, when executed by a machine, to cause the machine to generate a representation of an apparatus. The apparatus includes a bridge agent, a first interconnect, and a second interconnect. The bridge agent is configured by bridge control signals to control transmission of a communication between the first interconnect and the second interconnect. The representation may be a sequence of instructions written in a programming language to mimic in a computer simulation environment attributes derived from a projected fabricated hardware instance of the apparatus.

摘要翻译： 对于具有存储在其上的指令的机器可读介质描述了装置，系统和方法的实施例，当由机器执行时，该机器可读介质使机器产生装置的表示。 该装置包括桥接器，第一互连和第二互连。 桥接代理由桥控制信号配置，以控制第一互连和第二互连之间的通信的传输。 该表示可以是以编程语言编写的指令序列，以在计算机模拟环境中模仿从该装置的投影制造的硬件实例导出的属性。