公开(公告)号：US20060095752A1

公开(公告)日：2006-05-04

申请号：US10711159

申请日：2004-08-28

申请人： Min-Cheng Kao

发明人： Min-Cheng Kao

IPC分类号： G06F9/00

CPC分类号： G06F9/3806 ,  G06F9/30054 ,  G06F9/4486

摘要： A method and device for return instruction prediction in microprocessors and digital signal processors. The method and device uses a return target buffer, in which a return instruction address table serves to store addresses of return instructions, and a return target stack is used to store target pointers of return instructions, thereby correct prediction results can be provided in the fetch stage of a pipeline.

摘要翻译： 一种用于微处理器和数字信号处理器中的返回指令预测的方法和装置。 方法和装置使用返回目标缓冲器，其中返回指令地址表用于存储返回指令的地址，并且使用返回目标栈来存储返回指令的目标指针，从而可以在提取中提供校正预测结果 管道的阶段

公开(公告)号：US20060095721A1

公开(公告)日：2006-05-04

申请号：US11046555

申请日：2005-01-31

申请人： Stuart Biles ,  Krisztian Flautner ,  Scott Mahlke ,  Nathan Clark

发明人： Stuart Biles ,  Krisztian Flautner ,  Scott Mahlke ,  Nathan Clark

IPC分类号： G06F15/00

CPC分类号： G06F9/3885 ,  G06F8/44 ,  G06F9/3005 ,  G06F9/30054 ,  G06F9/3806 ,  G06F9/3836 ,  G06F9/3897

摘要： An accelerator 120 is tightly coupled to the normal execution unit 110. The operand store, which could be a register file 130, a stack based operand store or other operand store is shared by the execution unit and the accelerator unit. Operands may also be accessed as immediate values within the instructions themselves. The sequences of individual program instructions corresponding to computational subgraphs remain within a program but can be recognized by the accelerator as suitable for acceleration and when encountered are executed by the accelerator instead of by the normal execution unit. Within such tightly coupled arrangement problems can arise due to a lack of register resources within the system. The present technique provides that at least some intermediate operand values which are generated within the accelerator, but are determined not to be referenced outside of the computational subgraph concerned, are not written to the operand store.

摘要翻译： 加速器120紧密耦合到正常执行单元110。 执行单元和加速器单元共享作为寄存器文件130的操作数存储器，基于栈的操作数存储或其他操作数存储。 操作数也可以在指令本身内作为立即值访问。 与计算子图相对应的单独程序指令的顺序保持在程序内，但是可被加速器识别为适合于加速，并且当遇到由加速器而不是由正常执行单元执行时。 在这种紧密耦合的布置中，由于系统内缺少寄存器资源，可能会出现问题。 本技术提供了在加速器内生成但被确定不被引用到有关的计算子图之外的至少一些中间操作数值不被写入操作数存储。

公开(公告)号：US20060095720A1

公开(公告)日：2006-05-04

申请号：US11044734

申请日：2005-01-28

申请人： Stuart Biles ,  Krisztian Flautner ,  Scott Mahlke ,  Nathan Clark

发明人： Stuart Biles ,  Krisztian Flautner ,  Scott Mahlke ,  Nathan Clark

IPC分类号： G06F15/00

CPC分类号： G06F9/3885 ,  G06F8/433 ,  G06F8/44 ,  G06F9/30043 ,  G06F9/3005 ,  G06F9/30054 ,  G06F9/3017 ,  G06F9/30174 ,  G06F9/3806 ,  G06F9/3897

摘要： There is provided an information processor for executing a program comprising a plurality of separate program instructions: processing logic operable to individually execute said separate program instructions of said program; an operand store operable to store operand values; and an accelerator having an array comprising a plurality of functional units, said accelerator being operable to execute a combined operation corresponding to a computational subgraph of said separate program instructions by configuring individual ones of said plurality of functional units to perform particular processing operations associated with one or more processing stages of said combined operation; wherein said accelerator executes said combined operation in dependence upon operand mapping data providing a mapping between operands of said combined operation and storage locations within said operand store and in dependence upon separately specified configuration data providing a mapping between said plurality of functional units and said particular processing operations such that said configuration data can be re-used for different operand mappings.

摘要翻译： 提供了一种用于执行程序的信息处理器，该程序包括多个单独的程序指令：可操作以单独执行所述程序的所述单独的程序指令的处理逻辑; 可操作地存储操作数值的操作数存储器; 以及具有包括多个功能单元的阵列的加速器，所述加速器可操作以通过配置所述多个功能单元中的各个功能单元执行与一个功能单元相关联的特定处理操作来执行对应于所述单独程序指令的计算子图的组合操作 或更多的处理阶段; 其中所述加速器根据操作数映射数据执行所述组合操作，所述操作数映射数据提供所述组合操作的操作数与所述操作数存储之间的存储位置之间的映射，并且依赖于提供所述多个功能单元之间的映射和所述特定处理 使得所述配置数据可以被重新用于不同的操作数映射的操作。

公开(公告)号：US07010665B1

公开(公告)日：2006-03-07

申请号：US10185513

申请日：2002-06-27

申请人： Bret L. Toll ,  Michael J. St. Clair ,  John Allan Miller ,  Hitesh Ahuja

发明人： Bret L. Toll ,  Michael J. St. Clair ,  John Allan Miller ,  Hitesh Ahuja

IPC分类号： G06F12/02

CPC分类号： G06F9/322 ,  G06F9/30003 ,  G06F9/30054 ,  G06F9/3016 ,  G06F9/30167 ,  G06F9/3017 ,  G06F9/30178 ,  G06F9/324 ,  G06F9/342 ,  G06F9/3557 ,  G06F9/383

摘要： A method and apparatus for decompressing relative addresses. A compressed relative address is retrieved from one or more micro-operation entries of a micro-operation storage and an uncompressed relative address is reconstructed from the compressed relative address and an instruction pointer (IP) address associated with the head of the micro-operation storage line in which the compressed relative address was stored. IP-relative addresses may be computed in a manner similar to relative branch targets, then compressed and stored in one or more micro-operation entries of a micro-operation storage line to be reconstructed later according to an IP address associated with the respective micro-operation storage line in which their compressed counterpart was stored.

公开(公告)号：US20060026410A1

公开(公告)日：2006-02-02

申请号：US10995158

申请日：2004-11-24

申请人： Megumi Yokoi ,  Masaki Ukai

发明人： Megumi Yokoi ,  Masaki Ukai

IPC分类号： G06F9/44

CPC分类号： G06F9/3806 ,  G06F9/30054

摘要： A return address in response to a return instruction corresponding to a call instruction is stored in a return address stack when a branch history detects presence of the call instruction. When the branch history detects the presence of the return instruction before a branch reservation station completes executing the call instruction, the return address in response to the return instruction is not stored in the return address stack. If so, an output selection circuit predicts a correct return target using information stored in the return address stack.

摘要翻译： 当分支历史检测到呼叫指令的存在时，响应于与呼叫指令相对应的返回指令的返回地址被存储在返回地址堆栈中。 当分支历史在分支保留站完成执行呼叫指令之前检测到返回指令的存在时，响应于返回指令的返回地址不存储在返回地址堆栈中。 如果是，则输出选择电路使用存储在返回地址堆栈中的信息来预测正确的返回目标。

公开(公告)号：US06968446B1

公开(公告)日：2005-11-22

申请号：US09927058

申请日：2001-08-09

申请人： Kevin J. McGrath

发明人： Kevin J. McGrath

IPC分类号： G06F9/00

CPC分类号： G06F9/30054 ,  G06F9/30094 ,  G06F9/30101 ,  G06F9/30112 ,  G06F9/3013 ,  G06F9/30138 ,  G06F9/30185 ,  G06F9/30189 ,  G06F9/342

摘要： A processor is configured to support a programmable flags masking during processing of a system call instruction such as Syscall. The processor includes a register storing a mask, where an indication within the mask corresponds to each of a plurality of flags used by the processor. Based on the state of the indication, the processor may clear a corresponding flag or may retain the value of the corresponding flag. By programming the register appropriately, the desired clearing and retaining of the plurality of flags may be performed as part of the system call instruction. Flexibility may be provided for different operating systems having different sets of flags to be preserved or cleared.

摘要翻译： 处理器被配置为在系统调用指令（例如Syscall）的处理期间支持可编程标志屏蔽。 处理器包括存储掩模的寄存器，其中掩码内的指示对应于处理器使用的多个标志中的每一个。 基于指示的状态，处理器可以清除相应的标志，或者可以保留相应标志的值。 通过适当地对寄存器进行编程，可以作为系统调用指令的一部分来执行所希望的多个标志的清除和保持。 可以为具有不同标志组的不同操作系统提供灵活性，以保持或清除。

公开(公告)号：US06931632B2

公开(公告)日：2005-08-16

申请号：US10005302

申请日：2001-11-08

申请人： Vinodha Ramasamy ,  Jenn-Yuan Tsai

发明人： Vinodha Ramasamy ,  Jenn-Yuan Tsai

IPC分类号： G06F9/32 ,  G06F9/38 ,  G06F9/44 ,  G06F9/45 ,  G06F15/00

CPC分类号： G06F9/30054 ,  G06F9/30072 ,  G06F9/3842 ,  G06F9/3853

摘要： Method and apparatus for instrumentation of an executable computer program that includes a predicated branch-call instruction followed by a call-shadow instruction. The predicated branch-call instruction and the call-shadow instruction is stored in a first bundle of instructions, which is followed by a second bundle. The predicated branch-call instruction is changed to a predicated branch instruction that targets a fifth bundle of instructions, and the predicate of the predicated branch instruction is the same as the predicate of the predicated branch-call instruction. Third, fourth, and fifth bundles are created to preserve program semantics. The third bundle is inserted following the first bundle and includes the call-shadow instruction. The fourth bundle is inserted following the third bundle and includes a branch instruction that targets the second bundle. The fifth bundle is inserted following the fourth bundle and includes a branch-call instruction that has a target address equal to the target address of the predicated branch-call instruction. Instrumentation instructions are then inserted.

摘要翻译： 用于仪器化可执行计算机程序的方法和装置，其包括一个预先指派的分支调用指令，后跟一个调用 - 阴影指令。 预测的分支调用指令和调用指令被存储在第一指令束中，随后是第二束。 预测的分支调用指令被改变为目标第五指令束的预测分支指令，并且预测分支指令的谓词与预测分支调用指令的谓词相同。 创建第三，第四和第五个包以保留程序语义。 第三个软件包按照第一个软件包插入，并包含调用阴影指令。 第四个捆绑包插入第三个捆绑包之后，并包括一个分支指令，目标是第二个捆绑包。 第五束被插入到第四束之后，并且包括具有等于预测分支呼叫指令的目标地址的目标地址的分支调用指令。 然后插入仪器说明。

公开(公告)号：US20050172110A1

公开(公告)日：2005-08-04

申请号：US11046453

申请日：2005-01-28

申请人： Teppei Hirotsu ,  Yuuichi Abe ,  Takeshi Kataoka ,  Yasuhiro Nakatsuka

发明人： Teppei Hirotsu ,  Yuuichi Abe ,  Takeshi Kataoka ,  Yasuhiro Nakatsuka

IPC分类号： G06F9/38 ,  G06F9/30 ,  G06F9/32 ,  G06F9/42 ,  G06F9/46 ,  G06F9/48

CPC分类号： G06F9/30054 ,  G06F9/3804 ,  G06F9/382

摘要： A high-performance information processing technique permitting updating of an instruction buffer ready for effective prefetching to branch instructions and returning to the subroutine with a small volume of hardware is to be provided at low cost. It is an information processing apparatus equipped with a CPU, a memory, prefetch means and the like, wherein a prefetch address generator unit in the prefetch means decodes a branching series of instructions including at least one branched address calculating instruction and branching instruction to a branched address out of a current instruction buffer storing the series of instructions currently accessed by the CPU, and thereby looks ahead to the branching destination address. The information processing apparatus further comprises a RTS instruction buffer for storing a series of instructions of the return destinations of RTS instructions, and series of instructions stored in the current instruction buffer are saved into the RTS instruction buffer.

摘要翻译： 能够以低成本提供允许更新准备好用于有效预取到分支指令并且以少量硬件返回到子程序的指令缓冲器的高性能信息处理技术。 它是配备有CPU，存储器，预取装置等的信息处理装置，其中预取装置中的预取地址发生器单元将包含至少一个分支地址计算指令和分支指令的分支指令序列解码为分支 从存储CPU当前访问的一系列指令的当前指令缓冲器中寻址，从而期待分支目的地址。 信息处理装置还包括RTS指令缓冲器，用于存储RTS指令的返回目的地的一系列指令，存储在当前指令缓冲器中的一系列指令被保存到RTS指令缓冲器中。

公开(公告)号：US06910119B1

公开(公告)日：2005-06-21

申请号：US09598713

申请日：2000-06-21

申请人： Jonathan P. Douglas

发明人： Jonathan P. Douglas

IPC分类号： G06F9/00 ,  G06F9/30 ,  G06F9/32 ,  G06F9/38

CPC分类号： G06F9/3885 ,  G06F9/30054 ,  G06F9/30101 ,  G06F9/3806 ,  G06F9/3836

摘要： In a system where multiple instruction pipes share access to a common return stack buffer (RSB), coordination is provided to ensure that no instruction pipe gains unfair access to the RSB. Additionally, further coordination control may be provided to ensure that a pipe operates upon valid data notwithstanding communication delays that may be present in a communication path between the pipe and the RSB. In one embodiment, if a system must gain access to the RSB, it determines with reference to prior accesses to the RSB whether immediate access the RSB would exceed a predetermined access rate. If so, it delays its attempt to access the RSB until it re-synchronizes to the access rate. In another embodiment, it delays use of data from the RSB until communication delays are overcome.

摘要翻译： 在多个指令管道共享访问公共返回堆栈缓冲区（RSB）的系统中，提供了协调，以确保没有指令管道获得对RSB的不公平访问。 此外，可以提供进一步的协调控制以确保管道在有效数据的情况下运行，尽管可能存在于管道和RSB之间的通信路径中的通信延迟。 在一个实施例中，如果系统必须获得对RSB的访问，则其参考对RSB的先前访问来确定RSB的即时访问是否将超过预定访问速率。 如果是这样，它会延迟访问RSB的尝试，直到它重新同步到访问速率。 在另一个实施例中，它延迟来自RSB的数据的使用，直到克服了通信延迟。

公开(公告)号：US20050055544A1

公开(公告)日：2005-03-10

申请号：US10900537

申请日：2004-07-28

申请人： Ute Gaertner ,  Erwin Pfeffer ,  Charles Webb

发明人： Ute Gaertner ,  Erwin Pfeffer ,  Charles Webb

IPC分类号： G06F9/32 ,  G06F15/00

CPC分类号： G06F9/30054 ,  G06F9/30058

摘要： The present invention relates to a central processing unit comprising: (a) a number of functional units (A, B, . . . , N), (b) at least one module for processing of a function call received from one of the functional units, the module having a decoder to obtain an instruction address from the function call, a memory for storing a plurality of control instructions and for storing a plurality of branch instructions, each control instruction having an assigned instruction address for a next instruction and each branch instruction having assigned at least two alternative instruction addresses for a next instruction, first logic circuitry for processing of the branch instructions in order to select one of the at least two alternative instruction addresses of one of the branch instructions, second logic circuitry for processing of the control instructions in order to return a result in response to the function call.

摘要翻译： 本发明涉及一种中央处理单元，包括：（a）多个功能单元（A，B，...，N），（b）至少一个模块，用于处理从功能性 单元，该模块具有从功能调用获得指令地址的解码器，用于存储多个控制指令并存储多个分支指令的存储器，每个控制指令具有分配的下一个指令的指令地址和每个分支 为下一个指令分配了至少两个备选指令地址的指令，第一逻辑电路，用于处理分支指令以便选择一个分支指令的至少两个备选指令地址之一;第二逻辑电路，用于处理 控制指令，以便响应函数调用返回结果。