公开(公告)号：US20060095722A1

公开(公告)日：2006-05-04

申请号：US11048663

申请日：2005-01-31

申请人： Stuart Biles ,  Krisztian Flautner ,  Scott Mahlke ,  Nathan Clark

发明人： Stuart Biles ,  Krisztian Flautner ,  Scott Mahlke ,  Nathan Clark

IPC分类号： G06F15/00

CPC分类号： G06F8/4441

摘要： There is provided an apparatus for processing data under control of a program having program instructions and subgraph suggestion information identifying respective sequences of program instructions corresponding to computational subgraphs identified within said program, said apparatus comprising: a memory operable to store a program formed of separate program instructions; processing logic operable to execute respective separate program instructions from said program; and accelerator logic operable in response to reaching an execution point within said program associated with a subgraph suggestion to execute a sequence of program instructions corresponding to said subgraph suggestion as an accelerated operation instead of executing said sequence of program instructions as respective separate program instructions with said processing logic.

摘要翻译： 提供了一种用于在具有程序指令和子图建议信息的程序的控制下处理数据的装置，该子图表建议信息识别与所述程序中识别的计算子图相对应的程序指令的相应序列，所述装置包括：存储器，可操作以存储由单独程序形成的程序 说明书 处理逻辑可操作以从所述程序执行相应的单独的程序指令; 以及加速器逻辑，其可操作以响应于到达与子图建议相关联的所述程序内的执行点，以执行对应于所述子图建议的程序指令序列作为加速操作，而不是执行所述程序指令序列作为具有所述 处理逻辑。

公开(公告)号：US20070239969A1

公开(公告)日：2007-10-11

申请号：US11806907

申请日：2007-06-05

申请人： Stuart Biles ,  Krisztian Flautner ,  Scott Mahlke ,  Nathan Clark

发明人： Stuart Biles ,  Krisztian Flautner ,  Scott Mahlke ,  Nathan Clark

IPC分类号： G06F9/305

CPC分类号： G06F8/4441

摘要： There is provided an apparatus for processing data under control of a program having program instructions and subgraph suggestion information identifying respective sequences of program instructions corresponding to computational subgraphs identified within said program, said apparatus comprising: a memory operable to store a program formed of separate program instructions; processing logic operable to execute respective separate program instructions from said program; and accelerator logic operable in response to reaching an execution point within said program associated with a subgraph suggestion to execute a sequence of program instructions corresponding to said subgraph suggestion as an accelerated operation instead of executing said sequence of program instructions as respective separate program instructions with said processing logic.

摘要翻译： 提供了一种用于在具有程序指令和子图建议信息的程序的控制下处理数据的装置，该子图表建议信息识别与所述程序中识别的计算子图相对应的程序指令的相应序列，所述装置包括：存储器，可操作以存储由单独程序形成的程序 说明书 处理逻辑可操作以从所述程序执行相应的单独的程序指令; 以及加速器逻辑，其可操作以响应于到达与子图建议相关联的所述程序内的执行点，以执行对应于所述子图建议的程序指令序列作为加速操作，而不是执行所述程序指令序列作为具有所述 处理逻辑。

公开(公告)号：US20060095721A1

公开(公告)日：2006-05-04

申请号：US11046555

申请日：2005-01-31

申请人： Stuart Biles ,  Krisztian Flautner ,  Scott Mahlke ,  Nathan Clark

发明人： Stuart Biles ,  Krisztian Flautner ,  Scott Mahlke ,  Nathan Clark

IPC分类号： G06F15/00

CPC分类号： G06F9/3885 ,  G06F8/44 ,  G06F9/3005 ,  G06F9/30054 ,  G06F9/3806 ,  G06F9/3836 ,  G06F9/3897

摘要： An accelerator 120 is tightly coupled to the normal execution unit 110. The operand store, which could be a register file 130, a stack based operand store or other operand store is shared by the execution unit and the accelerator unit. Operands may also be accessed as immediate values within the instructions themselves. The sequences of individual program instructions corresponding to computational subgraphs remain within a program but can be recognized by the accelerator as suitable for acceleration and when encountered are executed by the accelerator instead of by the normal execution unit. Within such tightly coupled arrangement problems can arise due to a lack of register resources within the system. The present technique provides that at least some intermediate operand values which are generated within the accelerator, but are determined not to be referenced outside of the computational subgraph concerned, are not written to the operand store.

摘要翻译： 加速器120紧密耦合到正常执行单元110。 执行单元和加速器单元共享作为寄存器文件130的操作数存储器，基于栈的操作数存储或其他操作数存储。 操作数也可以在指令本身内作为立即值访问。 与计算子图相对应的单独程序指令的顺序保持在程序内，但是可被加速器识别为适合于加速，并且当遇到由加速器而不是由正常执行单元执行时。 在这种紧密耦合的布置中，由于系统内缺少寄存器资源，可能会出现问题。 本技术提供了在加速器内生成但被确定不被引用到有关的计算子图之外的至少一些中间操作数值不被写入操作数存储。

公开(公告)号：US20060095720A1

公开(公告)日：2006-05-04

申请号：US11044734

申请日：2005-01-28

申请人： Stuart Biles ,  Krisztian Flautner ,  Scott Mahlke ,  Nathan Clark

发明人： Stuart Biles ,  Krisztian Flautner ,  Scott Mahlke ,  Nathan Clark

IPC分类号： G06F15/00

CPC分类号： G06F9/3885 ,  G06F8/433 ,  G06F8/44 ,  G06F9/30043 ,  G06F9/3005 ,  G06F9/30054 ,  G06F9/3017 ,  G06F9/30174 ,  G06F9/3806 ,  G06F9/3897

摘要： There is provided an information processor for executing a program comprising a plurality of separate program instructions: processing logic operable to individually execute said separate program instructions of said program; an operand store operable to store operand values; and an accelerator having an array comprising a plurality of functional units, said accelerator being operable to execute a combined operation corresponding to a computational subgraph of said separate program instructions by configuring individual ones of said plurality of functional units to perform particular processing operations associated with one or more processing stages of said combined operation; wherein said accelerator executes said combined operation in dependence upon operand mapping data providing a mapping between operands of said combined operation and storage locations within said operand store and in dependence upon separately specified configuration data providing a mapping between said plurality of functional units and said particular processing operations such that said configuration data can be re-used for different operand mappings.

摘要翻译： 提供了一种用于执行程序的信息处理器，该程序包括多个单独的程序指令：可操作以单独执行所述程序的所述单独的程序指令的处理逻辑; 可操作地存储操作数值的操作数存储器; 以及具有包括多个功能单元的阵列的加速器，所述加速器可操作以通过配置所述多个功能单元中的各个功能单元执行与一个功能单元相关联的特定处理操作来执行对应于所述单独程序指令的计算子图的组合操作 或更多的处理阶段; 其中所述加速器根据操作数映射数据执行所述组合操作，所述操作数映射数据提供所述组合操作的操作数与所述操作数存储之间的存储位置之间的映射，并且依赖于提供所述多个功能单元之间的映射和所述特定处理 使得所述配置数据可以被重新用于不同的操作数映射的操作。

公开(公告)号：US20050283593A1

公开(公告)日：2005-12-22

申请号：US10870548

申请日：2004-06-18

申请人： Vladimir Vasekin ,  Andrew Rose ,  Stuart Biles

发明人： Vladimir Vasekin ,  Andrew Rose ,  Stuart Biles

IPC分类号： G06F9/00 ,  G06F9/38

CPC分类号： G06F9/3848

摘要： A branch prediction mechanism within a pipelined processing apparatus uses a history value HV which records preceding branch outcomes in either a first mode or a second mode. In the first mode respective bits within the history value represent a mixture of branch taken and branch not taken outcomes. In the second mode a count value within the history value indicates a count of a contiguous sequence of branch taken outcomes.

摘要翻译： 流水线处理装置内的分支预测机构使用历史值HV，其以第一模式或第二模式记录先前分支结果。 在第一个模式中，历史值中的各个位表示分支取和分支未采取结果的混合。 在第二模式中，历史值内的计数值表示分支采取结果的连续序列的计数。

公开(公告)号：US20050066131A1

公开(公告)日：2005-03-24

申请号：US10668373

申请日：2003-09-24

申请人： Stuart Biles ,  Christopher Dornan ,  Vladimir Vasekin ,  Andrew Rose

发明人： Stuart Biles ,  Christopher Dornan ,  Vladimir Vasekin ,  Andrew Rose

IPC分类号： G06F9/312 ,  G06F9/38 ,  G06F12/00 ,  G06F12/02

CPC分类号： G06F12/023 ,  G06F9/30043 ,  G06F9/383

摘要： An apparatus and method for loading data values from a memory system are provided. The data processing apparatus comprises a data processing unit operable to execute instructions, and a register file having a plurality of registers operable to store data values accessible by the data processing unit when executing the instructions. Further, a holding register is provided which does not form one of a working set of registers of the register file, and is operable to temporarily store a data value, the holding register having a data portion for storing the data value, and an identifier portion operable to store identifier data associated with the data value. The data processing unit is then responsive to a preload instruction to issue a preload memory access request to a memory system to cause a data value identified by the preload instruction to be located in the memory system, and dependent on predetermined criteria to cause a copy of that data value along with associated identifier data to be loaded from the memory system into the holding register. Furthermore, the data processing unit is responsive to a load instruction to cause a comparison operation to be performed to determine whether identifier data derived from the load instruction matches the identifier data in the identifier portion of the holding register. If it does, the data value stored in the holding register is made available to the data processing unit without requiring a memory access request to be issued to the memory system. Only in the event of there being no match does the memory access request get issued to the memory system to cause a data value identified by the load instruction to be made available to the data processing unit from the memory system.

摘要翻译： 提供了一种用于从存储器系统加载数据值的装置和方法。 数据处理装置包括可操作以执行指令的数据处理单元和具有多个寄存器的寄存器文件，其可操作以在执行指令时存储由数据处理单元可访问的数据值。 此外，提供一个保持寄存器，其不形成寄存器堆的寄存器的工作组之一，并且可操作以临时存储数据值，具有用于存储数据值的数据部分的保持寄存器和标识符部分 可操作地存储与数据值相关联的标识符数据。 数据处理单元然后响应于预加载指令向存储器系统发出预加载存储器访问请求，以使得由预加载指令识别的数据值位于存储器系统中，并且依赖于预定标准，以使得 该数据值以及要从存储器系统加载到保持寄存器中的相关联的标识符数据。 此外，数据处理单元响应于加载指令以执行比较操作，以确定从加载指令导出的标识符数据是否与保持寄存器的标识符部分中的标识符数据匹配。 如果是这样，则保存寄存器中存储的数据值可用于数据处理单元，而不需要向存储器系统发出存储器访问请求。 只有在没有匹配的情况下，存储器访问请求被发送到存储器系统才能使由加载指令识别的数据值从存储器系统提供给数据处理单元。

公开(公告)号：US20080071953A1

公开(公告)日：2008-03-20

申请号：US11898640

申请日：2007-09-13

申请人： Daniel Kershaw ,  Stuart Biles

发明人： Daniel Kershaw ,  Stuart Biles

IPC分类号： G06F13/36 ,  G06F15/177

CPC分类号： G06F12/1416 ,  G06F12/1491

摘要： A data processing apparatus and method for generating access requests is provided. A bus master is provided which can operate either in a secure domain or a non-secure domain of the data processing apparatus, according to a signal received from external to the bus master. The signal is generated to be fixed during normal operation of the bus master. Control logic is provided which, when the bus master device is operating in a secure domain, is operable to generate a domain specifying signal associated with an access request generated by the bus master core indicating either secure or non-secure access, in dependence on either a default memory map or securely defined memory region descriptors. Thus, the bus master operating in a secure domain can generate both secure and non-secure accesses, without itself being able to switch between secure and non-secure operation.

摘要翻译： 提供了一种用于产生访问请求的数据处理装置和方法。 根据从总线主机外部接收的信号，提供可以在数据处理装置的安全域或非安全域中操作的总线主机。 在总线主机的正常工作期间，生成固定信号。 提供控制逻辑，当总线主设备在安全域中操作时，可以根据总线主机核心生成的指示安全或非安全访问的访问请求产生一个域指定信号， 默认内存映射或安全定义的内存区域描述符。 因此，在安全域中操作的总线主机可以生成安全和非安全访问，而无需在安全和非安全操作之间切换。

公开(公告)号：US20050071722A1

公开(公告)日：2005-03-31

申请号：US10912103

申请日：2004-08-06

申请人： Stuart Biles

发明人： Stuart Biles

IPC分类号： G06F12/08 ,  G06F11/00 ,  G06F11/30 ,  G06F12/16 ,  G08C25/00 ,  G11C29/00 ,  H03M13/00 ,  H04L1/00

CPC分类号： G06F11/004 ,  G06F12/0802

摘要： The present invention provides a data processing apparatus and method for handling corrupted data values. The method comprises the steps of: a) accessing a data value in a memory within a data processing apparatus; b) initiating processing of the data value within the data processing apparatus; c) whilst at least one of the steps a) and b) are being performed, determining whether the data value accessed is corrupted; and d) when it is determined that the data value is corrupted, disabling an interface used to propagate data values between the data processing apparatus and a device coupled to the data processing apparatus to prevent propagation of a corrupted data value to the device. When a data value is accessed, the data processing apparatus can begin processing of that data value and, hence, the performance of the data processing apparatus is not reduced. If it is determined that the data value which was accessed was corrupted or contains an error then the interface which couples the data processing apparatus with the device is disabled. Disabling the interface effectively quarantines any corrupted data values by preventing them from being propagated to the device. Preventing corrupted data values from being propagated to the device ensures that no change in state can occur in the device as a result of the corrupted data values.

摘要翻译： 本发明提供一种用于处理损坏的数据值的数据处理装置和方法。 该方法包括以下步骤：a）访问数据处理设备内的存储器中的数据值; b）启动数据处理装置内的数据值的处理; c）在执行步骤a）和b）中的至少一个时，确定所访问的数据值是否被破坏; 以及d）当确定数据值被破坏时，禁用用于在数据处理设备和耦合到数据处理设备的设备之间传播数据值的接口，以防止损坏的数据值传播到设备。 当访问数据值时，数据处理装置可以开始处理该数据值，因此数据处理装置的性能不会降低。 如果确定所访问的数据值被破坏或包含错误，则将数据处理设备与设备耦合的接口被禁用。 禁用接口通过防止它们传播到设备来有效隔离任何损坏的数据值。 防止损坏的数据值传播到设备，确保由于损坏的数据值，设备中不会发生状态改变。

公开(公告)号：US20050005072A1

公开(公告)日：2005-01-06

申请号：US10788315

申请日：2004-03-01

申请人： Julie-Anne Pruvost ,  Norbert Lataille ,  Stuart Biles

发明人： Julie-Anne Pruvost ,  Norbert Lataille ,  Stuart Biles

IPC分类号： G06F12/08 ,  G06F12/00

CPC分类号： G06F12/0831

摘要： Within a coherent multi-processing system multiple processor cores 4, 6 are coupled via respective memory buses to a memory access control unit 16. The memory buses are formed of a uni-processing portion containing signals specifying a memory access request in accordance with a uni-processing protocol. This uni-processing bus is augmented by a multi-processing bus containing signals giving additional information concerning memory access requests which may be used by the memory access control unit to service those requests and manage coherency within the system.

摘要翻译： 在相干多处理系统中，多个处理器核心4,6经由相应的存储器总线耦合到存储器访问控制单元16.存储器总线由包含指定根据uni的存储器访问请求的信号的单处理部分形成 处理协议。 这种单处理总线由包含信号的多处理总线增加，该信号提供关于存储器访问请求的附加信息，存储器访问控制单元可以由存储器访问控制单元使用来为这些请求提供服务并且管理系统内的一致性。

公开(公告)号：US20080091884A1

公开(公告)日：2008-04-17

申请号：US11907265

申请日：2007-10-10

申请人： Frederic Piry ,  Philippe Raphalen ,  Norbert Lataille ,  Stuart Biles ,  Richard Grisenthwaite

发明人： Frederic Piry ,  Philippe Raphalen ,  Norbert Lataille ,  Stuart Biles ,  Richard Grisenthwaite

IPC分类号： G06F12/00

CPC分类号： G06F12/0831

摘要： A data processing apparatus and method are provided for handling write access requests to shared memory. The data processing apparatus has a plurality of processing units for performing data processing operations requiring access to data in shared memory, with each processing unit having a cache associated therewith for storing a subset of the data for access by that processing unit. Cache coherency logic is provided that employs a cache coherency protocol to ensure data accessed by each processing unit is up-to-date. Each processing unit will issue a write access request when outputting a data value for storing in the shared memory, and when the write access request is of a type requiring both the associated cache and the shared memory to be updated, a coherency operation is initiated within the cache coherency logic. The coherency operation is then performed in respect of all of the caches associated with the plurality of processing units, including the cache associated with the processing unit that issued the write access request, in order to ensure that the data in those caches is kept coherent. The cache coherency logic is further operable to issue an update request to the shared memory in respect of the data value the subject of the write access request. Such a technique provides a particularly simple and efficient mechanism for ensuring the correct behaviour of such write access requests, without impacting the complexity and access timing of the originating processing unit and its associated cache.

摘要翻译： 提供了一种用于处理对共享存储器的写访问请求的数据处理装置和方法。 数据处理装置具有多个处理单元，用于执行需要访问共享存储器中的数据的数据处理操作，每个处理单元具有与其相关联的高速缓冲存储器，用于存储用于该处理单元访问的数据的子集。 提供了缓存一致性逻辑，其使用高速缓存一致性协议来确保每个处理单元访问的数据是最新的。 当输出用于存储在共享存储器中的数据值时，每个处理单元将发出写入访问请求，并且当写入访问请求是要求更新相关联的高速缓存和共享存储器的类型时，在第 高速缓存一致性逻辑。 然后关于与多个处理单元相关联的所有高速缓存执行一致性操作，包括与发出写访问请求的处理单元相关联的高速缓存，以便确保这些高速缓存中的数据保持一致。 高速缓存一致性逻辑还可用于相对于写访问请求的对象的数据值向共享存储器发出更新请求。 这种技术提供了一种用于确保这种写入访问请求的正确行为的特别简单和有效的机制，而不影响始发处理单元及其相关联的高速缓存的复杂性和访问定时。