公开(公告)号：US20100118424A1

公开(公告)日：2010-05-13

申请号：US12267234

申请日：2008-11-07

Applicant: Bruce Douglas Buch ,  Mathew P. Vea ,  Jon Karsten Klarqvist

Inventor： Bruce Douglas Buch ,  Mathew P. Vea ,  Jon Karsten Klarqvist

IPC: G11B27/36

CPC classification number: G11B20/22 ,  G11B20/10009 ,  G11B20/10046 ,  G11B20/10194 ,  G11B20/10222 ,  G11B20/10481 ,  G11B2220/2516

Abstract: A method and apparatus for measuring latency in a communication path is provided. The technique includes driving a signal such as a square wave on the communication path, such as a write path such that it travels around the write-read path, and sensing a returned signal at one end of the write-read path. A square wave signal corresponding to the square wave driven on the write path is delayed by a predetermined phase thus generating a delayed signal. The returned signal and the delayed signal are mixed, producing a mixed signal. The mixed signal is integrated to obtain an integrated output. The phase by which the delayed signal is shifted is successively adjusted. Returned signals are mixed with such delayed signals until the integrated output is equal to zero. The phase shift amount that results in a nulled integrated output, less a quarter cycle of the square wave, is equal to the round trip latency of the write-read path.

Abstract translation: 提供了一种用于测量通信路径中的等待时间的方法和装置。 该技术包括在通信路径上驱动诸如方波的信号，例如写入路径，使得其绕写入读取路径传播，并且感测读写路径的一端的返回信号。 对应于在写入路径上驱动的方波的方波信号被延迟预定的相位，从而产生延迟的信号。 返回信号和延迟信号混合，产生混合信号。 混合信号被集成以获得集成输出。 相继调整延迟信号移位的相位。 返回的信号与这样的延迟信号混合，直到积分输出等于零。 导致无效的积分输出的相移量少于方波的四分之一周期，等于写入读取路径的往返延迟。

公开(公告)号：US20100091398A1

公开(公告)日：2010-04-15

申请号：US12648746

申请日：2009-12-29

Applicant: William Gene Bliss ,  Thomas V. Souvignier

Inventor： William Gene Bliss ,  Thomas V. Souvignier

IPC: G11B27/36 ,  G11B21/02

CPC classification number: G11B5/09 ,  G11B20/10009 ,  G11B20/10046 ,  G11B20/10222 ,  G11B20/10425 ,  G11B2220/2516

Abstract: A system reads data from a magnetic storage media. A read head reads data from the magnetic storage media and produce an analog signal. A variable gain amplifier amplifies the analog signal. An offset adjust module substantially centers the amplified analog signal to a midscale. A Magneto Resistive Asymmetry (MRA) correction module MRA corrects the amplified analog signal. A Continuous Time Filter (CTF) compensation module processes the amplified analog signal. An Analog to Digital Converter (ADC) samples the amplified analog signal based upon a control signal to produce a digital signal. A Disk Lock Clock (DLC) system produces the control signal to the ADC. The control signal is representative of a frequency offset caused by at least one servo wedge rate error. A Finite Impulse Response (FIR) filter module filters the digital signal. A sequence detector processes the digital signal and detects a bit sequence from the digital signal.

Abstract translation: 系统从磁存储介质读取数据。 读头从磁存储介质读取数据并产生模拟信号。 可变增益放大器放大模拟信号。 偏移调整模块将放大的模拟信号基本上居中， 磁阻非对称（MRA）校正模块MRA校正放大的模拟信号。 连续时间滤波器（CTF）补偿模块处理放大的模拟信号。 模数转换器（ADC）根据控制信号对放大的模拟信号进行采样以产生数字信号。 磁盘锁定时钟（DLC）系统产生到ADC的控制信号。 控制信号表示由至少一个伺服楔速率误差引起的频率偏移。 有限脉冲响应（FIR）滤波器模块对数字信号进行滤波。 序列检测器处理数字信号并从数字信号中检测位序列。

公开(公告)号：US07688687B2

公开(公告)日：2010-03-30

申请号：US11667299

申请日：2006-07-18

Applicant: Kouji Okamoto ,  Akira Yamamoto ,  Hiroki Mouri

Inventor： Kouji Okamoto ,  Akira Yamamoto ,  Hiroki Mouri

IPC: G11B7/085

CPC classification number: G11B20/10009 ,  G11B20/10046 ,  G11B20/10222 ,  G11B20/1403 ,  G11B2020/1476 ,  G11B2220/2562 ,  H03L7/091 ,  H03L7/1976 ,  H04L7/02 ,  H04L7/033

Abstract: In a feedforward timing extractor for extracting timing information from a playback signal, a frequency ratio calculation section 2 calculates the ratio between the frequency of the playback signal and the frequency of the output clock of a frequency synthesizer 6 by utilizing a specific pattern and a specific pattern appearing interval in the playback signal. A control section 4 controls the frequency dividing rate of the frequency synthesizer 6 in such a manner that the frequency ratio calculated by the frequency ratio calculation section 2 has a set value. Thus, as compared with a case in which the output clock of the frequency synthesizer 6 is a high-frequency fixed-rate clock, it is not necessary to operate the digital circuits at high speeds. Consequently, even in cases where the playback frequency (the playback rate) of the signal changes with time, the decimation rate at which pulses of a fixed clock are eliminated is constant, thereby reducing power consumption.

Abstract translation: 在从再现信号中提取定时信息的前馈定时提取器中，频率比计算部分2通过利用特定的模式和特定的模式来计算重放信号的频率与频率合成器6的输出时钟的频率之间的比率 重放信号中的图案出现间隔。 控制部分4以频率比计算部分2计算出的频率比具有设定值的方式控制频率合成器6的分频率。 因此，与频率合成器6的输出时钟为高频固定速度时钟的情况相比，不需要以高速操作数字电路。 因此，即使在信号的重放频率（播放速度）随时间变化的情况下，消除固定时钟的脉冲的抽取率恒定，从而降低功耗。

公开(公告)号：US20100066722A1

公开(公告)日：2010-03-18

申请号：US12531441

申请日：2007-11-13

Applicant: Hiroki Mouri

Inventor： Hiroki Mouri

IPC: H04L7/02 ,  G06F3/038

CPC classification number: G11B20/10009 ,  G11B20/10046 ,  G11B20/10055 ,  G11B20/10222 ,  G11B20/10287 ,  G11B20/1403 ,  G11B2220/2541 ,  G11B2220/2545 ,  G11B2220/2562

Abstract: In an asynchronous read channel system, a reference value interpolation-type maximum likelihood decoder ASML having a small circuit scale (e.g., seven taps) is employed. A nonlinear waveform the equalizer SEQ is provided before the maximum likelihood decoder ASML. The nonlinear waveform the equalizer SEQ includes an FIR filter having, for example, four taps, and performs nonlinear waveform equalization with respect to an input digital signal so that only signal components having small amplitudes and high frequencies are amplified. After the nonlinear waveform equalization, the signal is input to the reference value interpolation-type maximum likelihood decoder ASML, which performs maximum likelihood decoding with respect to the signal. Therefore, even when the reference value interpolation-type maximum likelihood decoder includes a smaller number of taps and thus has a small circuit scale, maximum likelihood decoding with a high error correction function can be performed.

Abstract translation: 在异步读通道系统中，采用具有小电路规模（例如，7个抽头）的参考值内插型最大似然解码器ASML。 非线性波形在最大似然解码器ASML之前提供均衡器SEQ。 非线性波形均衡器SEQ包括具有例如四个抽头的FIR滤波器，并且相对于输入数字信号执行非线性波形均衡，使得仅具有小幅度和高频率的信号分量被放大。 在非线性波形均衡之后，信号被输入到参考值内插型最大似然解码器ASML，其对该信号执行最大似然解码。 因此，即使当参考值内插型最大似然解码器包括较少数量的抽头，因此具有小的电路规模时，也可以执行具有高纠错功能的最大似然解码。

公开(公告)号：US20100020250A1

公开(公告)日：2010-01-28

申请号：US12526746

申请日：2007-11-01

Applicant: Kouji Okamoto ,  Akira Yamamoto ,  Hiroki Mouri ,  Yoshinori Shirakawa

Inventor： Kouji Okamoto ,  Akira Yamamoto ,  Hiroki Mouri ,  Yoshinori Shirakawa

IPC: H04N5/66 ,  H04N5/95

CPC classification number: H04L7/0331 ,  G11B20/10009 ,  G11B20/10037 ,  G11B20/10222 ,  G11B20/14 ,  G11B2020/1287 ,  G11B2220/2541 ,  G11B2220/2545 ,  G11B2220/2562 ,  H03L7/06

Abstract: In a feedforward control type reproduced signal processor, a clock generator 1 changes a clock frequency, depending on a digital value set by a digital value generator 7. Therefore, power consumption of a system is optimized and control is facilitated. Moreover, when a frequency lock state is established in which a frequency ratio calculated by a frequency ratio calculator 3 satisfies a set condition, a modulation component having a small change is generated using a clock of a clock generator 1. Therefore, the digital value is updated with the modulation component, so that a change in clock frequency of the clock generator 1 gradually varies. As a result, the influence of the change in clock frequency on the response of a decoding process is reduced.

Abstract translation: 在前馈控制型再现信号处理器中，时钟发生器1根据由数字值发生器7设定的数字值改变时钟频率。因此，优化了系统的功耗并且便于控制。 此外，当频率锁定状态被建立，其中由频率比计算器3计算的频率比满足设定条件时，使用时钟发生器1的时钟产生具有小变化的调制分量。因此，数字值为 用调制分量更新，使得时钟发生器1的时钟频率的变化逐渐变化。 结果，降低了时钟频率的变化对解码处理的响应的影响。

公开(公告)号：US20090316561A1

公开(公告)日：2009-12-24

申请号：US12485131

申请日：2009-06-16

Applicant: Koichiro Nishimura ,  Yusuke Nakamura

Inventor： Koichiro Nishimura ,  Yusuke Nakamura

IPC: G11B7/135

CPC classification number: G11B20/10009 ,  G11B7/00456 ,  G11B7/1267 ,  G11B20/10046 ,  G11B20/10055 ,  G11B20/10194 ,  G11B20/10212 ,  G11B20/10222 ,  G11B20/10481

Abstract: When a phase shift is to be evaluated, based on a difference between an output from a waveform equalization circuit to equalize an input reproduced signal to a predetermined target equalization characteristic and the target equalization characteristic, the phase shift of the reproduced signal relative to a channel clock, a group delay characteristic with respect to the frequency of the waveform equalization circuit is fixed. Hence, an equalized waveform as an output from the waveform equalization circuit can preserve phase shift information of the inputted reproduced signal to correctly detect the phase shift of the reproduced waveform using the equalized waveform. It is hence possible to realize, with high precision, optimal value learning of various parameters for the recording, reproduction, and servo by use of the phase shift as an index.

Abstract translation: 当要评估相移时，基于来自波形均衡电路的输出之间的差以将输入再现信号均衡到预定的目标均衡特性和目标均衡特性，再现信号相对于通道的相移 时钟，相对于波形均衡电路的频率的组延迟特性是固定的。 因此，作为来自波形均衡电路的输出的均衡波形可以保存输入的再现信号的相移信息，以使用均衡波形来正确地检测再现波形的相移。 因此，通过使用相移作为指标，可以高精度地实现用于记录，再现和伺服的各种参数的最佳值学习。

公开(公告)号：US20090316552A1

公开(公告)日：2009-12-24

申请号：US12453546

申请日：2009-05-14

Applicant: Toshiaki Kitano

Inventor： Toshiaki Kitano

IPC: G11B20/10 ,  G01R29/00 ,  G06F19/00

CPC classification number: G01R25/005 ,  G11B20/10 ,  G11B20/10037 ,  G11B20/10222 ,  G11B20/14 ,  G11B2220/2545 ,  G11B2220/2562

Abstract: A time interval analyzer includes a phase comparator which decides whether a measured signal contains a delay quantity for either a positive delay or a negative delay relative to a characteristic value, and a processor circuit which outputs a ratio of a number of the measured signals containing the positive delay and a number of the measured signals containing the negative delay.

Abstract translation: 时间间隔分析器包括相位比较器，该相位比较器确定测量信号是否包含相对于特性值的正延迟或负延迟的延迟量，以及处理器电路，其输出包含 正延迟和包含负延迟的测量信号的数量。

公开(公告)号：US20090310941A1

公开(公告)日：2009-12-17

申请号：US12543509

申请日：2009-08-19

Applicant: John L. Melanson ,  Mark P. Rygh

Inventor： John L. Melanson ,  Mark P. Rygh

IPC: H04N7/00

CPC classification number: H04N5/76 ,  G11B20/10037 ,  G11B20/10222 ,  G11B20/10425 ,  G11B20/10527 ,  G11B20/14 ,  G11B20/225 ,  G11B2020/00065 ,  G11B2220/2562 ,  H04N9/8211

Abstract: A method of operating an electronic video device such as a DVD player, wherein video clock signals and audio clock signals are derived from a system clock signal using two phase-lock loops, and these video and audio clock signals are used to process encoded video data and encoded audio data, but digital-to-analog conversion of the audio data stream is controlled by the system clock signal rather than the audio clock signals. By using the system clock signal to control the audio digital-to-analog converter (DAC), the DAC avoids the poor performance issues that can arise from jitter introduced into the audio clock signals by the PLL. The system clock signal may be divided by an integer to generate the sampling clock for the audio DAC. In the illustrative embodiment, the system clock signal has a rate which is not an integer multiple of the sample rate of the audio data stream.

Abstract translation: 一种操作诸如DVD播放器的电子视频设备的方法，其中使用两个锁相环从系统时钟信号导出视频时钟信号和音频时钟信号，并且这些视频和音频时钟信号用于处理编码视频数据 和编码音频数据，但音频数据流的数模转换由系统时钟信号而不是音频时钟信号控制。 通过使用系统时钟信号来控制音频数/模转换器（DAC），DAC避免了由PLL引入到音频时钟信号中的抖动引起的性能问题。 系统时钟信号可以被除以整数以产生用于音频DAC的采样时钟。 在说明性实施例中，系统时钟信号具有不是音频数据流的采样率的整数倍的速率。

公开(公告)号：US07623586B2

公开(公告)日：2009-11-24

申请号：US10532468

申请日：2003-10-20

Applicant: Harumitsu Miyashita ,  Takeshi Nakajima ,  Naohiro Kimura

Inventor： Harumitsu Miyashita ,  Takeshi Nakajima ,  Naohiro Kimura

IPC: H04L23/02 ,  H04L5/12

CPC classification number: G11B27/3027 ,  G11B20/10009 ,  G11B20/10037 ,  G11B20/10055 ,  G11B20/10222 ,  G11B20/10425 ,  G11B2020/1288 ,  G11B2220/2541 ,  G11B2220/2562 ,  H03L7/091 ,  H03L7/107 ,  H04L7/033 ,  H04L7/041

Abstract: A frequency and phase control apparatus includes an analog/digital conversion section for converting a reproduction signal into a multiple bit digital signal based on a clock signal; a maximum likelihood decoding section for converting the multiple bit digital signal into a binary signal; a pattern detection section for detecting a pattern of the binary signal; and a determination section for determining whether or not the multiple bit digital signal and the clock signal are in synchronization with each other based on the detection result. When the determination result of the determination section indicates that the multiple bit digital signal and the clock signal are in synchronization with each other, the maximum likelihood decoding section generates a binary signal based on a first state transition rule; otherwise, the maximum likelihood decoding section generates a binary signal based on a second state transition rule.

Abstract translation: 频率相位控制装置包括：模拟/数字转换部分，用于基于时钟信号将再现信号转换成多位数字信号; 最大似然解码部分，用于将多位数字信号转换成二进制信号; 模式检测部分，用于检测二进制信号的模式; 以及确定部分，用于基于检测结果确定多位数字信号和时钟信号是否彼此同步。 当确定部分的确定结果指示多位数字信号和时钟信号彼此同步时，最大似然解码部分基于第一状态转换规则产生二进制信号; 否则，最大似然解码部分基于第二状态转换规则生成二进制信号。

公开(公告)号：US20090285061A1

公开(公告)日：2009-11-19

申请号：US12466219

申请日：2009-05-14

Applicant: YUTAKA NAGAI

Inventor： YUTAKA NAGAI

IPC: G11B19/02

CPC classification number: G11B20/14 ,  G11B19/02 ,  G11B20/10222 ,  G11B20/18 ,  G11B2020/10981 ,  G11B2020/1222 ,  G11B2020/1244

Abstract: A technique capable of realizing a power saving in a device for reproducing/recording digital signals by properly controlling a frequency of a clock. The device for reproducing/recording digital signals (device for reproducing an optical disk) includes: a difference comparing circuit for comparing a first parameter (demodulating block counter) updated each time a process for one correcting block is done in a demodulating circuit with a second parameter (error correcting block counter) updated each time a process of one correcting block is done in an error correcting circuit; and a circuit (clock controlling circuit etc.) for switching a frequency of a master clock (MCLK) depending on a comparison result of the difference comparing circuit. Thereby, the frequency of the clock can be switched both of when the demodulation for one correcting block is ended and when the correcting process for one correcting block is ended by using the switched master clock.

Abstract translation: 一种能够通过适当地控制时钟的频率来实现用于再现/记录数字信号的装置中的省电的技术。 用于再现/记录数字信号的设备（用于再现光盘的设备）包括：差分比较电路，用于比较每当在解调电路中进行一个校正块的处理时更新的第一参数（解调块计数器） 每当在纠错电路中完成一个校正块的处理时更新参数（纠错块计数器）; 以及用于根据差分比较电路的比较结果切换主时钟（MCLK）的频率的电路（时钟控制电路等）。 因此，当一个校正块的解调结束时和当通过使用切换的主时钟结束一个校正块的校正处理时，可以切换时钟的频率。