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公开(公告)号：US07876517B2
公开(公告)日：2011-01-25
申请号：US12267234
申请日：2008-11-07
IPC分类号： G11B5/09
CPC分类号： G11B20/22 , G11B20/10009 , G11B20/10046 , G11B20/10194 , G11B20/10222 , G11B20/10481 , G11B2220/2516
摘要： A method and apparatus for measuring latency in a communication path is provided. The technique includes driving a signal such as a square wave on the communication path, such as a write path such that it travels around the write-read path, and sensing a returned signal at one end of the write-read path. A square wave signal corresponding to the square wave driven on the write path is delayed by a predetermined phase thus generating a delayed signal. The returned signal and the delayed signal are mixed, producing a mixed signal. The mixed signal is integrated to obtain an integrated output. The phase by which the delayed signal is shifted is successively adjusted. Returned signals are mixed with such delayed signals until the integrated output is equal to zero. The phase shift amount that results in a nulled integrated output, less a quarter cycle of the square wave, is equal to the round trip latency of the write-read path.
摘要翻译： 提供了一种用于测量通信路径中的等待时间的方法和装置。 该技术包括在通信路径上驱动诸如方波的信号，例如写入路径，使得其绕写入读取路径传播，并且感测读写路径的一端的返回信号。 对应于在写入路径上驱动的方波的方波信号被延迟预定的相位，从而产生延迟的信号。 返回信号和延迟信号混合，产生混合信号。 混合信号被集成以获得集成输出。 相继调整延迟信号移位的相位。 返回的信号与这样的延迟信号混合，直到积分输出等于零。 导致无效的积分输出的相移量少于方波的四分之一周期，等于写入读取路径的往返延迟。
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公开(公告)号：US20100118424A1
公开(公告)日：2010-05-13
申请号：US12267234
申请日：2008-11-07
IPC分类号： G11B27/36
CPC分类号： G11B20/22 , G11B20/10009 , G11B20/10046 , G11B20/10194 , G11B20/10222 , G11B20/10481 , G11B2220/2516
摘要： A method and apparatus for measuring latency in a communication path is provided. The technique includes driving a signal such as a square wave on the communication path, such as a write path such that it travels around the write-read path, and sensing a returned signal at one end of the write-read path. A square wave signal corresponding to the square wave driven on the write path is delayed by a predetermined phase thus generating a delayed signal. The returned signal and the delayed signal are mixed, producing a mixed signal. The mixed signal is integrated to obtain an integrated output. The phase by which the delayed signal is shifted is successively adjusted. Returned signals are mixed with such delayed signals until the integrated output is equal to zero. The phase shift amount that results in a nulled integrated output, less a quarter cycle of the square wave, is equal to the round trip latency of the write-read path.
摘要翻译： 提供了一种用于测量通信路径中的等待时间的方法和装置。 该技术包括在通信路径上驱动诸如方波的信号，例如写入路径，使得其绕写入读取路径传播，并且感测读写路径的一端的返回信号。 对应于在写入路径上驱动的方波的方波信号被延迟预定的相位，从而产生延迟的信号。 返回信号和延迟信号混合，产生混合信号。 混合信号被集成以获得集成输出。 相继调整延迟信号移位的相位。 返回的信号与这样的延迟信号混合，直到积分输出等于零。 导致无效的积分输出的相移量少于方波的四分之一周期，等于写入读取路径的往返延迟。
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公开(公告)号：US07911724B2
公开(公告)日：2011-03-22
申请号：US12475001
申请日：2009-05-29
申请人： Bruce Douglas Buch , Mathew P. Vea
发明人： Bruce Douglas Buch , Mathew P. Vea
IPC分类号： G11B5/09
CPC分类号： G11B5/59655 , B82Y10/00 , G11B5/743 , G11B5/746 , G11B20/10009 , G11B20/10222 , G11B20/10425 , G11B20/10481 , G11B20/14 , G11B2005/0005 , G11B2020/1275 , G11B2220/2516
摘要： A technique is described for write synchronization phase calibration for storage media (e.g., bit patterned media). In one embodiment, a calibration write clock signal may be generated at a frequency offset from a nominal dot frequency of a bit patterned storage media. A periodic signal that was written to the media synchronous to the calibration write clock signal may then be read and mixed with a reference periodic signal at the nominal dot frequency to obtain a difference signal. This difference signal may be demodulated to determine a phase correction for write synchronization to the media.
摘要翻译： 描述了用于存储介质（例如，位图形介质）的写入同步相位校准的技术。 在一个实施例中，校准写时钟信号可以以与位图形存储介质的标称点频率偏移的频率产生。 然后可以将与校准写入时钟信号同步的写入媒体的周期性信号读取并以标称点频率与参考周期信号混合，以获得差分信号。 该差分信号可以被解调以确定用于与介质的写入同步的相位校正。
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公开(公告)号：US20100202079A1
公开(公告)日：2010-08-12
申请号：US12475001
申请日：2009-05-29
申请人： Bruce Douglas Buch , Mathew P. Vea
发明人： Bruce Douglas Buch , Mathew P. Vea
IPC分类号： G11B5/09
CPC分类号： G11B5/59655 , B82Y10/00 , G11B5/743 , G11B5/746 , G11B20/10009 , G11B20/10222 , G11B20/10425 , G11B20/10481 , G11B20/14 , G11B2005/0005 , G11B2020/1275 , G11B2220/2516
摘要： A technique is described for write synchronization phase calibration for storage media (e.g., bit patterned media). In one embodiment, a calibration write clock signal may be generated at a frequency offset from a nominal dot frequency of a bit patterned storage media. A periodic signal that was written to the media synchronous to the calibration write clock signal may then be read and mixed with a reference periodic signal at the nominal dot frequency to obtain a difference signal. This difference signal may be demodulated to determine a phase correction for write synchronization to the media.
摘要翻译： 描述了用于存储介质（例如，位图形介质）的写入同步相位校准的技术。 在一个实施例中，校准写时钟信号可以以与位图形存储介质的标称点频率偏移的频率产生。 然后可以将与校准写入时钟信号同步的写入媒体的周期性信号读取并以标称点频率与参考周期信号混合，以获得差分信号。 该差分信号可以被解调以确定用于与介质的写入同步的相位校正。
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公开(公告)号：US20100118427A1
公开(公告)日：2010-05-13
申请号：US12267215
申请日：2008-11-07
申请人： Bruce Douglas Buch , Mathew P. Vea
发明人： Bruce Douglas Buch , Mathew P. Vea
IPC分类号： G11B5/09
CPC分类号： G11B5/09 , B82Y10/00 , G11B5/59616 , G11B5/743
摘要： Clock synchronization techniques are described for data storage media, particularly for the tolerances of efficient use of bit patterned media (BPM) capacity. In particular, techniques are described where position of a read-write head and timing of a write and/or read clock is determined within a fraction of a dot of the underlying media. The techniques obviate the requirement for the fields conventionally written preceding a data sector to provide bit synchronization and symbol framing (sector synchronization fields).
摘要翻译： 为数据存储介质描述了时钟同步技术，特别是针对有效使用位图形介质（BPM）容量的公差。 特别地，描述了技术，其中读写头的位置和写入和/或读取时钟的定时在底层介质的点的一小部分内被确定。 该技术避免了对数据扇区之前传统写入的字段提供位同步和符号成帧（扇区同步字段）的要求。
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公开(公告)号：US20100118426A1
公开(公告)日：2010-05-13
申请号：US12267168
申请日：2008-11-07
CPC分类号： G11B5/59616 , B82Y10/00 , G11B5/09 , G11B5/743
摘要： A write clock control system comprises a clock controller that determines a phase offset based on a phase difference between a write clock signal and a media pattern corresponding to a given timing synchronization field being read, and a phase interpolator that produces an updated write clock signal by updating the phase of the write clock signal in accordance with control signals that are based on the phase offset signal.
摘要翻译： 写时钟控制系统包括时钟控制器，时钟控制器基于写时钟信号和对应于正在读取的给定定时同步字段的媒体模式之间的相位差来确定相位偏移;以及相位插值器，其通过以下步骤产生更新的写时钟信号： 根据基于相位偏移信号的控制信号更新写时钟信号的相位。
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公开(公告)号：US06412088B1
公开(公告)日：2002-06-25
申请号：US09453164
申请日：1999-12-02
申请人： Ara Patapoutian , Michael D. Leis , Mathew P. Vea
发明人： Ara Patapoutian , Michael D. Leis , Mathew P. Vea
IPC分类号： G11C2900
CPC分类号： G11B20/18 , G11B20/1876 , G11B2020/183
摘要： Disclosed is a method and apparatus for increasing the reliability of a disk drive. A block of information is read from a storage medium to provide a first sample, which is stored. The method determines whether an uncorrectable error occurred during the reading, and when the error is determined to have occurred, the block of information is reread from the storage medium to provide an averaged sample, and the average sample is decoded. Further disclosed is a storage unit, which includes a reader for reading a block of information from a storage medium to provide a first sample and for storing said first sample. An error determining mechanism determines whether an uncorrectable error occurred during the reading and issues a command to the reader to re-read the block of information to provide a second sample when the uncorrectable error is determined. A processor receives and averages the first sample and the second sample and produces an averaged sample. A decoder decodes the average sample.
摘要翻译： 公开了一种用于增加磁盘驱动器的可靠性的方法和装置。 从存储介质读取信息块以提供被存储的第一样本。 该方法确定在读取期间是否发生不可纠正的错误，并且当确定发生错误时，从存储介质重新读取信息块以提供平均样本，并且对平均样本进行解码。 进一步公开的是一种存储单元，其包括用于从存储介质读取信息块以提供第一样本并用于存储所述第一样本的读取器。 错误确定机构确定在读取期间是否发生不可校正的错误，并且当确定不可校正的错误时向读者发出命令以重新读取信息块以提供第二样本。 处理器接收并平均第一样品和第二样品并产生平均样品。 解码器解码平均样本。
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公开(公告)号：US20120224277A1
公开(公告)日：2012-09-06
申请号：US13037764
申请日：2011-03-01
申请人： Philip L. Steiner , Nan-Hsiung Yeh , Mathew P. Vea
发明人： Philip L. Steiner , Nan-Hsiung Yeh , Mathew P. Vea
CPC分类号： G11B5/746 , G11B5/012 , G11B20/10296 , G11B20/10314 , G11B20/10509 , G11B2220/252
摘要： A data signal comprising an even component and an odd component with differing amplitudes is received at a main automatic gain controller (AGC). The even component is adjusted by a first interleaved AGC and the odd component is adjusted by a second interleaved AGC such that even and odd component amplitudes are substantially equal. Amplitude adjusted even and odd components are recombined to define a data signal with components having substantially equal amplitudes. The even and odd components can be generated by a read transducer moving relative to a magnetic storage medium comprising tracks defined by discrete and spaced-apart recording bits arranged in an interspersed pattern. A read channel separates the data signal into even and odd samples such that a gain can be independently adjusted for each of the even and odd samples to compensate for asymmetry between the even and odd samples.
摘要翻译： 在主自动增益控制器（AGC）处接收包括偶数分量和具有不同幅度的奇数分量的数据信号。 通过第一交错AGC调整偶数分量，并且通过第二交错AGC调整奇数分量，使得偶数和奇数分量幅度基本相等。 振幅调整的偶数和奇数分量被重新组合以定义具有基本相等振幅的分量的数据信号。 偶数和奇数分量可以通过相对于磁存储介质移动的读取换能器来生成，该磁存储介质包括以散布图案排列的由离散和间隔开的记录位限定的轨道。 读通道将数据信号分离为偶数和奇数样本，使得可以针对偶数和奇数样本中的每一个独立地调整增益，以补偿偶数和奇数样本之间的不对称性。
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公开(公告)号：US5862005A
公开(公告)日：1999-01-19
申请号：US724977
申请日：1996-10-03
申请人： Michael D. Leis , Ara Patapoutian , Mathew P. Vea , Richard M. Ehrlich , Kevin D. Fisher , James A. Henson , William R. Akin, Jr.
发明人： Michael D. Leis , Ara Patapoutian , Mathew P. Vea , Richard M. Ehrlich , Kevin D. Fisher , James A. Henson , William R. Akin, Jr.
IPC分类号： G11B20/14 , G11B5/55 , G11B5/596 , G11B20/10 , G11B20/18 , G11B21/08 , G11B21/10 , G11B27/30 , H03M13/23 , H04L25/49 , G11B5/02 , G11B5/09
CPC分类号： G11B20/10009 , G11B20/1833 , G11B21/083 , G11B27/3027 , G11B5/5526 , G11B5/59655 , G11B5/59688 , H04L25/4904 , G11B2220/20 , G11B5/59627 , G11B5/5965
摘要： A magnetic disk drive data storage disk defines recording tracks divided into data sectors by narrow servo spokes. A data sector lying between servo spokes is recorded with user data encoded in accordance with a code having a predetermined distance and user data code rate. Each servo spoke of the recording area has at least one servo information field encoded in a wide bi-phase code pattern. The disk drive further includes a synchronous sampling data detection channel having a data transducer head positioned by a servo-controlled actuator over the recording track, a preamplifier for receiving electrical analog signals magnetically induced by the data transducer head from flux transitions present in at least the servo information field, a digital sampler for synchronously sampling the electrical analog signals to produce digital samples, and wide bi-phase decoding circuitry coupled to receive digital samples from the synchronous sampling data detection channel for decoding the wide bi-phase code pattern.
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公开(公告)号：US4617427A
公开(公告)日：1986-10-14
申请号：US701288
申请日：1985-02-13
申请人： Mathew P. Vea , Vinita Gupta
发明人： Mathew P. Vea , Vinita Gupta
CPC分类号： H04Q1/457
摘要： In a telephone signalling detector of the cross-correlation type, samples from a selected communications channel are multiplied with sine and cosine coefficients of different frequencies. The resulting sine and cosine products for each frequency are separately accumulated over a period of time after which the accumulated results are each squared and then summed for the individual frequencies. A series of sums of squares is compared in accordance with predetermined tone detection parameters to determine the presence or absence of a signalling tone defined by the coefficients. In a telephone signalling detector intended to detect any of a large family of specified signalling tones in any of a plurality of channels, the square root value of each of the sums of squares is typically provided by digital circuitry for subsequent use in a processor which is operated to complete the tone detection function in accordance with program instructions. A cost reduced square root circuit provides the square root values from a look-up ROM (read-only-memory) on a prompt and regular basis. In the square root circuit a large sum of squares is shifted toward lesser significance and a smaller sum of squares is shifted toward greater significance by means of a logic controlled shift register. Thereafter only a central portion of the shift register content is used along with a corresponding shift record to periodically address the look-up ROM.
摘要翻译： 在互相关类型的电话信令检测器中，来自所选择的通信信道的采样与不同频率的正弦和余弦系数相乘。 每个频率的所得到的正弦和余弦乘积在一段时间内分别累积，之后累积结果各自平方，然后针对各个频率求和。 根据预定的音调检测参数来比较一系列平方和，以确定由系数定义的信令音的存在或不存在。 在旨在检测多个通道中的任何一个中的任何特定信令音调的任何一个的电话信令检测器中，每个平方和的平方根通常由数字电路提供，用于随后在处理器中使用 根据程序指令操作完成音调检测功能。 成本降低的平方根电路在快速和定期的基础上从查找ROM（只读存储器）提供平方根值。 在平方根电路中，通过逻辑控制的移位寄存器，大的平方和向着较小的显着性移动并且较小的平方和向着更大的显着性移动。 此后，只有移位寄存器内容的中心部分与相应的移位记录一起使用以周期性地寻址查找ROM。
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