公开(公告)号：US20180219964A1

公开(公告)日：2018-08-02

申请号：US15418908

申请日：2017-01-30

Applicant: DELL PRODUCTS, L.P.

Inventor： DONAL CARPENTER

IPC: H04L29/08 ,  H03M7/12

CPC classification number: H03M7/12 ,  H03M7/30 ,  H03M7/3088

Abstract: A method and information handling system (IHS) converts a globally unique identifier to an electronic data interchange document identifier. The method includes receiving a globally unique identifier and converting the globally unique identifier into 128 binary bits. The 128 binary bits are selectively separated to form groups of bits that translate to integers. Each integer is replaced with an assigned alphanumeric character selected from an alphanumeric character map to form an encoded alphanumeric string of characters for use as an electronic data interchange document identifier.

公开(公告)号：US20150204698A1

公开(公告)日：2015-07-23

申请号：US14414574

申请日：2013-07-08

Applicant: Sang Yong LEE

Inventor： Sang Yong Lee

IPC: G01D9/02 ,  G01D5/14 ,  G01D5/26 ,  H03M7/12

CPC classification number: G01D9/02 ,  G01D5/14 ,  G01D5/2454 ,  G01D5/26 ,  H03M7/12

Abstract: The present invention relates to a programmable location control encoder, wherein the encoder has a new function of combining a sequential control function to conventional rotary encoders. The present invention comprises: a rotary disk having an absolute location code indicative of each location, that is, an address code formed by a combination of binary numbers; an optical sensor for detecting said binary address code; a signal amplification unit for amplifying an output signal of the optical sensor; and a control circuit board for outputting a digital signal by using a signal outputted from the signal amplification unit. According to the present invention, it is possible to convert a partition angle or a location control code by configuring a software resolution, and to maximize work efficiency by combining a sequential control function to conventional rotary encoders.

Abstract translation: 本发明涉及一种可编程位置控制编码器，其中编码器具有将顺序控制功能与常规旋转编码器组合的新功能。 本发明包括：具有表示每个位置的绝对位置代码的旋转盘，即由二进制数的组合形成的地址码; 用于检测所述二进制地址码的光学传感器; 信号放大单元，用于放大光学传感器的输出信号; 以及控制电路板，用于通过使用从信号放大单元输出的信号输出数字信号。 根据本发明，可以通过配置软件分辨率来转换分配角度或位置控制代码，并且通过将顺序控制功能组合到常规旋转编码器来最大化工作效率。

公开(公告)号：US08818761B2

公开(公告)日：2014-08-26

申请号：US13059476

申请日：2009-08-21

Applicant: Boris Klabunde ,  Stefan Butzmann

Inventor： Boris Klabunde ,  Stefan Butzmann

IPC: G06F15/00 ,  H03M7/12

CPC classification number: H03F1/32 ,  H03F1/56 ,  H03F2200/171 ,  H03F2200/375 ,  H03F2200/421 ,  H03H19/004 ,  H03K5/088 ,  H03M1/1295

Abstract: A signal processor for removing at least one unintended signal component from an input signal (ua) is proposed. The signal processor includes a filter device (130) and a processing device (150). The filter device (130) filters the input signal (uâ) and generates a filtered signal (uf), which includes the unintended signal component to be removed. The processing device (150) generates an output signal (um), which indicates a deviation of the input signal (ua) from the filtered input signal (uf). By detecting the unintended signal component first an removing this component from the input signal (uâ), the input signal will not be manipulated directly but the unintended signal component in the input signal (uâ) will be compensated. This allows to remove the unintended component from the input signal (uâ) with less distortions of the interesting components in the input signal (uâ).

Abstract translation: 提出了一种用于从输入信号（ua）中去除至少一个非预期信号分量的信号处理器。 信号处理器包括滤波器装置（130）和处理装置（150）。 滤波器装置（130）对输入信号（u'）进行滤波并产生滤波信号（uf），其包括要去除的非预期信号分量。 处理装置（150）产生输出信号（um），其表示输入信号（ua）与滤波后的输入信号（uf）的偏差。 通过首先检测非预期信号分量，从输入信号（u）中移除该分量，输入信号将不被直接操纵，而输入信号（u）中的非预期信号分量将被补偿。 这允许通过输入信号（u）中感兴趣的分量的较少失真从输入信号（u）中移除非预期的分量。

公开(公告)号：US08803718B2

公开(公告)日：2014-08-12

申请号：US13422833

申请日：2012-03-16

Applicant: Rakhel Kumar Parida ,  Ankur Bal ,  Anil Kumar ,  Anupam Jain

Inventor： Rakhel Kumar Parida ,  Ankur Bal ,  Anil Kumar ,  Anupam Jain

IPC: H03M1/66 ,  H03M7/14 ,  H03M1/06 ,  H03M7/12 ,  H03M1/74

CPC classification number: H03M7/12 ,  H03M1/0665 ,  H03M1/0673 ,  H03M1/74 ,  H03M7/14

Abstract: A dynamic element matching (DEM) scheme is implemented in a crawling code generator for converting a b-bit binary input code into a (2b−1)-bit digital output code. A random generator determines for every conversion step a direction. A decimal difference between the current and previous binary input is calculated. The new crawling output code is determined based on the previous crawling output code, the direction and the decimal difference. The DEM scheme is used in a digital-to-analog converter such that the crawling output code switches digital-to-analog converting elements that output analog signals that are then summed to be the final analog signal.

Abstract translation: 用于将b位二进制输入代码转换为（2b-1）位数字输出代码的爬行码生成器中实现动态元素匹配（DEM）方案。 随机生成器确定每个转换步骤一个方向。 计算当前和前一个二进制输入之间的十进制差值。 新的爬行输出代码基于先前的爬行输出代码，方向和小数差来确定。 DEM方案用于数模转换器，使得爬行输出码切换输出模拟信号的数模转换元件，然后将模拟信号相加为最终的模拟信号。

公开(公告)号：US07924181B1

公开(公告)日：2011-04-12

申请号：US11551557

申请日：2006-10-20

Applicant: Bruce H. Lam ,  Douglas E. Solomon ,  Rohit Kumar Gupta

Inventor： Bruce H. Lam ,  Douglas E. Solomon ,  Rohit Kumar Gupta

IPC: H03M7/12

CPC classification number: H04N21/4305 ,  H04N21/439

Abstract: A system, method, and computer program product are provided for estimating a clock signal. Specifically, during use, a clock signal associated with an audio signal is digitally estimated.

Abstract translation: 提供了一种用于估计时钟信号的系统，方法和计算机程序产品。 具体地，在使用期间，与音频信号相关联的时钟信号被数字估计。

公开(公告)号：US20080238736A1

公开(公告)日：2008-10-02

申请号：US11729191

申请日：2007-03-27

Applicant: Sanu K. Mathew ,  Ram Krishnamurthy

Inventor： Sanu K. Mathew ,  Ram Krishnamurthy

IPC: H03M7/12

CPC classification number: H03M7/12

Abstract: Disclosed herein are various embodiments of circuitry and methods to convert from a binary value to a BCD value.

Abstract translation: 本文公开了将二进制值转换为BCD值的电路和方法的各种实施例。

公开(公告)号：US07342519B2

公开(公告)日：2008-03-11

申请号：US11418743

申请日：2006-05-04

Applicant: Yukio Miura ,  Noriyuki Honda ,  Hiroshi Ishikawa ,  Ryo Teramachi

Inventor： Yukio Miura ,  Noriyuki Honda ,  Hiroshi Ishikawa ,  Ryo Teramachi

IPC: H03M7/12

CPC classification number: H03M5/08

Abstract: A receiving device is provided. A pulse width is measured, it is selected whether a determination process is performed for a pulse width having the length of one bit in accordance with the measured value of the pulse width or a pulse width having the length of ½ bit, it is discriminated whether a current pulse edge is a pulse edge at the center of the bit or a pulse edge at the boundary between bits while considering the bit data right before the determined bit, and when it is determined that the current pulse edge is the pulse edge at the center of the bit, the bit data is determined by the rising edge or the falling edge of the pulse edge.

Abstract translation: 提供接收装置。 测量脉冲宽度，根据脉冲宽度的测量值或长度为1/2位的脉冲宽度来选择是否对具有一位长度的脉冲宽度执行确定处理，判别是否 当前脉冲沿是比特的中心处的脉冲边缘或位置边界之间的脉冲边缘，同时考虑在确定的位之前的位数据，并且当确定当前脉冲沿是在 位的中心，位数据由脉冲沿的上升沿或下降沿决定。

公开(公告)号：US07057538B1

公开(公告)日：2006-06-06

申请号：US11033371

申请日：2005-01-10

Applicant: Matthew M. D'Amore

Inventor： Matthew M. D'Amore

IPC: H03M7/12

CPC classification number: H04L27/2035

Abstract: An encoder circuit and a related method for its operation, in which digital encoding, such as differential phase-shift keyed (DPSK) encoding, is performed as a parallel operation on N bits at a time. Each encoded bit is both output in parallel with the others of the N bits and is coupled as an input to encode the immediately next bit in the input data stream. The Nth encoded bit is fed back to the first encoder stage for use in encoding the (N+1)th bit in the input stream. The encoder typically includes a serial-to-parallel converter at the encoder inputs, and a parallel-to-serial converter at the encoder outputs.

Abstract translation: 用于其操作的编码器电路及其相关方法，其中进行诸如差分相移键控（DPSK）编码的数字编码作为N位的并行操作。 每个编码的位都与N位中的其他位并行地输出，并且作为输入耦合以对输入数据流中的紧邻位进行编码。 第N / O编码比特被反馈到第一编码器级，用于对输入流中的第（N + 1）个第比特进行编码。 编码器通常包括编码器输入处的串并转换器，以及编码器输出处的并行到串行转换器。

公开(公告)号：US06975259B1

公开(公告)日：2005-12-13

申请号：US10922532

申请日：2004-08-20

Applicant: Henrik T. Jensen

Inventor： Henrik T. Jensen

IPC: H03M3/00 ,  H03M3/04 ,  H03M7/12

CPC classification number: H03M3/478

Abstract: A scaled input current is produced that substantially matches the full scale input of a CTΔτADC that substantially cancels an offset bias current component of the input current. A variable bias resistance value is coupled between the integrator input and one of a supply voltage and a circuit common. The method further includes integrating the input current to produce an integrated signal representing a time averaged value of the input current to substantially remove noise from a frequency band of interest. The integrated signal is produced to a quantizer to produce a feedback current that substantially cancels a quantization noise component in the digital representation of the scaled analog signal by coupling the digital representation of the scaled analog signal to a programmable digital switch wherein the programmable digital switch either sinks current from or sources current to the integrator input.

Abstract translation: 产生缩放的输入电流，其基本上匹配基本上抵消输入电流的偏移偏置电流分量的CTDeltatauADC的满量程输入。 可变偏置电阻值耦合在积分器输入和电源电压和电路公共之一之间。 该方法还包括积分输入电流以产生表示输入电流的时间平均值的积分信号，以从感兴趣的频带基本上去除噪声。 将积分信号产生到量化器，以产生反馈电流，该反馈电流通过将经缩放的模拟信号的数字表示耦合到可编程数字开关，其中可编程数字开关或者是可编程数字开关，基本上消除了缩放的模拟信号的数字表示中的量化噪声分量 从当前流向积分器输入的电流。

公开(公告)号：US06922165B2

公开(公告)日：2005-07-26

申请号：US10689825

申请日：2003-10-20

Applicant: Robert E. Seymour

Inventor： Robert E. Seymour

IPC: H03M1/10 ,  H03M1/80 ,  H03M7/12

CPC classification number: H03M1/1028 ,  H03M1/1014 ,  H03M1/804

Abstract: A method and circuit for gain and/or offset correction in a CDAC circuit are provided. The gain and/or offset correction can be realized by adjusting the sampling capacitance of a capacitor array, with a positive array of the CDAC circuit being trimmed for gain correction, and a negative array of the CDAC circuit being trimmed for offset correction. Accordingly, corrections to variations in gain and/or offset caused by process variations can be suitably addressed. To facilitate gain correction, an exemplary CDAC circuit comprising an N-bit capacitor array includes on the positive side of the capacitor array an additional capacitor configured to capture the sampling voltage. An exemplary CDAC circuit can also be configured to have one or more capacitors shifted out of the total capacitance of the capacitor array, and thus reduce the amount of charge stored during sampling. To facilitate offset correction, an exemplary CDAC circuit comprises a negative side having a capacitor array, wherein the CDAC circuit is configured to provide a desired amount of offset voltage through sampling of some of the capacitance in the negative side to a reference voltage, and sampling a remainder of the capacitance in the negative side to ground.

Abstract translation: 提供了一种用于CDAC电路中增益和/或偏移校正的方法和电路。 可以通过调整电容器阵列的采样电容来实现增益和/或偏移校正，其中CDAC电路的正阵列被修整以用于增益校正，并且修正CDAC电路的负阵列以进行偏移校正。 因此，可以适当地解决由过程变化引起的增益和/或偏移的变化的校正。 为了促进增益校正，包括N位电容器阵列的示例性CDAC电路在电容器阵列的正侧上包括被配置为捕获采样电压的附加电容器。 示例性CDAC电路还可以被配置为使一个或多个电容器移出电容器阵列的总电容之外，从而减少在采样期间存储的电荷量。 为了便于偏移校正，示例性CDAC电路包括具有电容器阵列的负侧，其中CDAC电路被配置为通过将负侧中的一些电容采样到参考电压来提供期望量的偏移电压，并且采样 剩余的电容在负侧接地。