公开(公告)号：US08879347B2

公开(公告)日：2014-11-04

申请号：US13453495

申请日：2012-04-23

申请人： Hung-Chiang Chen

发明人： Hung-Chiang Chen

IPC分类号： G11C5/14 ,  G11C16/22

CPC分类号： G11C16/10 ,  G11C16/225 ,  G11C16/30

摘要： A flash memory device. In one embodiment, the flash memory device comprises a flash memory, a diode, a controller, and a capacitor. The flash memory has a voltage source pin. The diode is coupled between a voltage source and the voltage source pin of the flash memory. The controller is coupled to the flash memory via a data bus. The capacitor is coupled between the voltage source pin of the flash memory and a ground, and supplies power to the flash memory to enable the flash memory to complete writing of at least one data page when the level of the voltage source is lowered.

摘要翻译： 闪存设备。 在一个实施例中，闪速存储器件包括闪速存储器，二极管，控制器和电容器。 闪存有一个电压源引脚。 二极管耦合在闪存的电压源和电压源引脚之间。 控制器经由数据总线耦合到闪速存储器。 电容器耦合在闪速存储器的电压源引脚和地之间，并且当电压源的电平降低时，向闪存提供电力以使得闪存能够完成至少一个数据页的写入。

公开(公告)号：US08827165B2

公开(公告)日：2014-09-09

申请号：US13039832

申请日：2011-03-03

申请人： David C. McClure ,  Sooping Saw ,  Robert Wadsworth

发明人： David C. McClure ,  Sooping Saw ,  Robert Wadsworth

IPC分类号： G06K19/06 ,  G11C16/22 ,  G11C16/20 ,  G11C17/16

CPC分类号： G11C16/20 ,  G11C16/22 ,  G11C17/16

摘要： An integrated circuit includes an output pad, an alarm output pad, and a test mode output pad. A first multi-bit register is programmable to store programmable data such as data that identifies a customer for whom the integrated circuit has been manufactured. A second multi-bit register is programmable to store customer specified threshold data. A first circuit selectively couples the first and second multi-bit registers to the output pad. The first circuit is operable responsive to the integrated circuit being placed into a test mode to perform parallel-to-serial conversion of either the customer identification data stored in the first multi-bit register or the customer specified threshold data stored in the second multi-bit register and drive the converted data for output through the output pad. The integrated circuit further includes a tamper detection circuit operable responsive to the customer specified threshold data to generate a tamper alarm signal. A second circuit selectively couples the tamper alarm signal to the alarm output pad and test mode output pad depending on whether the integrated circuit is in a test mode. More specifically, the second circuit operates to drive the alarm output pad with the tamper alarm signal when the integrated circuit is not in test mode and drive the test mode output pad with the tamper alarm signal when the integrated circuit is in test mode (with the alarm output pad driven to a known state).

摘要翻译： 集成电路包括输出焊盘，报警输出焊盘和测试模式输出焊盘。 第一个多位寄存器是可编程的，用于存储可编程数据，例如识别已经制造了集成电路的客户的数据。 可编程第二个多位寄存器来存储客户指定的阈值数据。 第一电路将第一和第二多位寄存器选择性地耦合到输出焊盘。 第一电路可操作地响应于集成电路被放置在测试模式中，以执行存储在第一多位寄存器中的客户识别数据或存储在第二多位寄存器中的客户指定的阈值数据的并行 - 串行转换， 位寄存器，并通过输出板驱动转换后的数据输出。 集成电路还包括可响应于客户指定的阈值数据操作的篡改检测电路，以产生篡改报警信号。 第二电路根据集成电路是否处于测试模式，选择性地将篡改报警信号耦合到报警输出焊盘和测试模式输出焊盘。 更具体地，当集成电路不处于测试模式时，第二电路用于驱动具有篡改报警信号的报警输出板，并且当集成电路处于测试模式时驱动具有篡改报警信号的测试模式输出板 报警输出板驱动到已知状态）。

公开(公告)号：US08804417B2

公开(公告)日：2014-08-12

申请号：US13157343

申请日：2011-06-10

申请人： Chan Park ,  Changseok Kang ,  Sung-Il Chang ,  Byeong-In Choe

发明人： Chan Park ,  Changseok Kang ,  Sung-Il Chang ,  Byeong-In Choe

IPC分类号： G11C16/04 ,  G11C16/06 ,  G11C16/08 ,  G11C16/10 ,  G11C16/12 ,  G11C16/22

CPC分类号： G11C16/10 ,  G11C16/3418

摘要： A nonvolatile memory device including a dummy memory cell and a method of programming the same, wherein the nonvolatile memory device includes a dummy memory cell, and a plurality of memory cells serially connected to the dummy memory cell. The nonvolatile memory device sets a voltage provided to the dummy memory cell according to a distance between a selected memory cell among the plurality of memory cells and the dummy memory cell when a program operation is performed.

摘要翻译： 一种包括虚拟存储单元的非易失性存储器件及其编程方法，其中非易失性存储器件包括一个虚拟存储单元和与该虚拟存储单元串联连接的多个存储单元。 非易失性存储装置根据执行程序操作时的多个存储单元中的所选择的存储单元与虚拟存储单元之间的距离，设定提供给虚拟存储单元的电压。

公开(公告)号：US08619472B2

公开(公告)日：2013-12-31

申请号：US13281312

申请日：2011-10-25

申请人： Hee Youl Lee

发明人： Hee Youl Lee

IPC分类号： G11C16/06 ,  G11C16/08 ,  G11C16/22

CPC分类号： G11C16/0483 ,  G11C16/10 ,  G11C16/3427

摘要： A method for operating a flash memory device includes applying a pass voltage to a drain pass word line, a source pass word line, and unselected word lines. The drain pass word line is provided between a drain select line and a word line. The drain pass word line has a structure in the same manner as the word lines. The source pass word line is provided between a source select line and a word line. The source pass word line has a structure in the same manner as the word lines. A program voltage is applied to a selected word line associated with a selected memory cell block. A ground voltage is applied to drain pass word lines and source pass word lines. Word lines associated with unselected memory cell blocks are set to a floating state.

摘要翻译： 一种用于操作闪速存储器件的方法包括将通过电压施加到漏极通过字线，源极字线和未选字线。 漏极通行字线设置在漏极选择线和字线之间。 漏极字线具有与字线相同的结构。 在源选择线和字线之间提供源通过字线。 源通道字线具有与字线相同的结构。 将编程电压施加到与所选择的存储器单元块相关联的选定字线。 接地电压被施加到漏通字线和源通路字线。 与未选择的存储单元块相关联的字线设置为浮动状态。

公开(公告)号：US08156280B2

公开(公告)日：2012-04-10

申请号：US13116433

申请日：2011-05-26

申请人： Hitoshi Kurosawa

发明人： Hitoshi Kurosawa

IPC分类号： G06F12/16 ,  G11C16/22

CPC分类号： G11C16/22 ,  G06F21/79 ,  G06F2221/2143

摘要： Receiving a request for canceling setting, a control circuit erases data stored in a corresponding block, changes a value of a protection flag, and cancels protection setting. When an overall protection is set for any block, the control circuit prohibits access to all blocks, except when it is an operation mode for activating a memory program contained in the microcomputer. Further, control circuit permits an access to a block M only when partial protection is set, CPU is in the mode for activating a memory program contained in the microcomputer and the access is for reading an instruction code in accordance with an instruction fetch.

摘要翻译： 接收到取消设置的请求，控制电路擦除存储在相应块中的数据，改变保护标志的值，并取消保护设置。 当为任何块设置整体保护时，控制电路禁止访问所有块，除非是用于激活包含在微型计算机中的存储器程序的操作模式。 此外，只有当设置了部分保护时，控制电路才允许对块M的访问，CPU处于用于激活包含在微型计算机中的存储器程序的模式，并且访问用于根据提取指令读取指令代码。

公开(公告)号：US08045372B2

公开(公告)日：2011-10-25

申请号：US11760767

申请日：2007-06-10

申请人： Hee Youl Lee

发明人： Hee Youl Lee

IPC分类号： G11C16/06 ,  G11C16/08 ,  G11C16/22

CPC分类号： G11C16/0483 ,  G11C16/10 ,  G11C16/3427

摘要： A flash memory device includes a plurality of memory cell blocks, an operating voltage generator, a block switching unit and a voltage supply circuit. Each of the plurality of memory cell blocks includes select lines and word lines, and has pass word lines included between the select lines and the word lines. The operating voltage generator outputs operating voltages to global select lines, global word lines and global pass word lines. The block switching unit connects the global word lines to the word lines and the select lines in response to a block select signal. The voltage supply circuit is connected to the select line and the pass word line, and is configured to supply the select line and the pass word line with a ground voltage in response to a block select inverse signal.

摘要翻译： 闪存器件包括多个存储单元块，工作电压发生器，块切换单元和电压供应电路。 多个存储单元块中的每一个都包括选择线和字线，并且具有包括在选择线和字线之间的字线。 工作电压发生器将工作电压输出到全局选择线，全局字线和全局通过字线。 块切换单元响应于块选择信号将全局字线连接到字线和选择线。 电压供给电路连接到选择线和通过字线，并且被配置为响应于块选择反相信号而将选择线和通过字线提供接地电压。

公开(公告)号：US07822914B2

公开(公告)日：2010-10-26

申请号：US12180666

申请日：2008-07-28

申请人： Hitoshi Kurosawa

发明人： Hitoshi Kurosawa

IPC分类号： G06F12/16 ,  G11C16/22

CPC分类号： G11C16/22 ,  G06F21/79 ,  G06F2221/2143

摘要： Receiving a request for canceling setting, a control circuit erases data stored in a corresponding block, changes a value of a protection flag, and cancels protection setting. When an overall protection is set for any block, the control circuit prohibits access to all blocks, except when it is an operation mode for activating a memory program contained in the microcomputer. Further, control circuit permits an access to a block M only when partial protection is set, CPU is in the mode for activating a memory program contained in the microcomputer and the access is for reading an instruction code in accordance with an instruction fetch.

摘要翻译： 接收到取消设置的请求，控制电路擦除存储在相应块中的数据，改变保护标志的值，并取消保护设置。 当为任何块设置整体保护时，控制电路禁止访问所有块，除非是用于激活包含在微型计算机中的存储器程序的操作模式。 此外，只有当设置了部分保护时，控制电路才允许对块M的访问，CPU处于用于激活包含在微型计算机中的存储器程序的模式，并且访问用于根据提取指令读取指令代码。

公开(公告)号：US20100002511A1

公开(公告)日：2010-01-07

申请号：US12443528

申请日：2007-09-27

申请人： Guoqiao Tao ,  Steven V. E. S. Van Dijk

发明人： Guoqiao Tao ,  Steven V. E. S. Van Dijk

IPC分类号： G11C16/22 ,  G11C16/02

CPC分类号： G11C16/22

摘要： The invention relates to a non-volatile memory device comprising: an input for providing external data (D1) to be stored on the non-volatile memory device; and a first non-volatile memory block (100) and a second non-volatile memory block (200), the first non-volatile memory block (100) and the second non-volatile memory block (200) being provided on a single die (10), wherein the first non-volatile memory block (100) and second non-volatile memory block (200) are of a different type such that the first non-volatile memory block (100) and the second non-volatile memory block (200) require incompatible external attack techniques in order to retrieve data there from, the external data (D1) being stored in a distributed way (D1′, D1″) into both the first non-volatile memory block (100) and the second non-volatile memory block (200). The invention further relates to method of protecting data in a non-volatile memory device.

摘要翻译： 本发明涉及一种非易失性存储器件，包括：用于提供要存储在非易失性存储器件上的外部数据（D1）的输入; 和第一非易失性存储器块（100）和第二非易失性存储器块（200），所述第一非易失性存储器块（100）和所述第二非易失性存储器块（200）设置在单个管芯 （10），其中第一非易失性存储器块（100）和第二非易失性存储器块（200）是不同类型的，使得第一非易失性存储器块（100）和第二非易失性存储器块 （200）需要不兼容的外部攻击技术以便从其中检索数据，外部数据（D1）以分布式方式（D1'，D1“）存储到第一非易失性存储器块（100）和 第二非易失性存储器块（200）。 本发明还涉及在非易失性存储器件中保护数据的方法。

公开(公告)号：US07616490B2

公开(公告)日：2009-11-10

申请号：US11550383

申请日：2006-10-17

申请人： Nima Mokhlesi ,  Masaaki Higashitani

发明人： Nima Mokhlesi ,  Masaaki Higashitani

IPC分类号： G11C16/04 ,  G11C16/06 ,  G11C16/10 ,  G11C16/12 ,  G11C16/22

CPC分类号： G11C16/0483 ,  G11C11/5628 ,  G11C16/3418 ,  G11C16/3427 ,  G11C16/3454 ,  G11C2211/5621 ,  H01L21/28114 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/42376 ,  H01L29/66825 ,  H01L29/7881

摘要： A select gate structure for a non-volatile storage system includes a select gate and a coupling electrode which are independently drivable. The coupling electrode is adjacent to a word line in a NAND string and has a voltage applied which reduces gate induced drain lowering (GIDL) program disturb of an adjacent unselected non-volatile storage element. In particular, an elevated voltage can be applied to the coupling electrode when the adjacent word line is used for programming. A reduced voltage is applied when a non-adjacent word line is used for programming. The voltage can also be set based on other programming criterion. The select gate is provided by a first conductive region while the coupling electrode is provided by a second conductive region formed over, and isolated from, the first conductive region.

摘要翻译： 用于非易失性存储系统的选择栅极结构包括独立驱动的选择栅极和耦合电极。 耦合电极与NAND串中的字线相邻，并且具有施加的电压，其减小相邻未选择的非易失性存储元件的栅极引起的漏极降低（GIDL）编程干扰。 特别地，当相邻字线用于编程时，可以将高电压施加到耦合电极。 当使用非相邻字线进行编程时，施加降低的电压。 电压也可以根据其他编程标准设定。 选择栅极由第一导电区域提供，而耦合电极由形成在第一导电区域上并与之隔离的第二导电区域提供。

公开(公告)号：US07145799B2

公开(公告)日：2006-12-05

申请号：US11170880

申请日：2005-06-30

申请人： Giovanni Naso ,  Pietro Piersimoni ,  Tommaso Vali

发明人： Giovanni Naso ,  Pietro Piersimoni ,  Tommaso Vali

IPC分类号： G11C16/22

CPC分类号： G11C7/24 ,  G11C16/22 ,  G11C2029/4402

摘要： An improved Flash memory device is described with a protection register lock bit erase enable circuit. A bond pad coupled to the lock bit erase enable circuit of the improved Flash memory is not bonded when the individual Flash memory chip wafer is packaged. This allows the memory manufacturer to access the bond pad and erase the lock bits while the chip is still in wafer form via a test card probe, but makes the lock bits effectively uneraseable when the chip wafer is packaged. This enables the memory chip manufacturer to enhance reliability and fault tolerance of the Flash memory device by thoroughly testing the lock bits and protection register functionality. Additionally, the lock bit erase enable circuit increases manufacturing flexibility by allowing the memory chip manufacturer to reprogram the protection register and lock bits in case of organizational changes or inadvertent or erroneous programming of the protection register.

摘要翻译： 用保护寄存器锁定位擦除使能电路描述改进的闪速存储器件。 当单独的闪存芯片晶片被封装时，耦合到改进的闪速存储器的锁定位擦除使能电路的接合焊盘不被接合。 这允许存储器制造商通过测试卡探针访问焊盘并擦除锁定位，同时芯片仍然是晶片形式，但是当芯片晶片被封装时，使得锁定位有效地不可靠。 这使得内存芯片制造商能够通过彻底测试锁定位和保护寄存器功能来增强闪存设备的可靠性和容错能力。 此外，锁定位擦除使能电路通过允许存储器芯片制造商在组织改变或保护寄存器的无意或错误编程的情况下重新编程保护寄存器和锁定位来提高制造灵活性。