公开(公告)号：US10157886B2

公开(公告)日：2018-12-18

申请号：US15437766

申请日：2017-02-21

申请人： Samsung Electro-Mechanics, Co., Ltd.

发明人： Dae Hyun Park ,  Eun Jung Jo ,  Sung Won Jeong ,  Han Kim ,  Mi Ja Han

IPC分类号： H01L23/02 ,  H01L25/065 ,  H01L23/00 ,  H01L23/31

摘要： A fan-out semiconductor package includes: a first interconnection member having a through-hole; a first semiconductor chip disposed in the through-hole and having an active surface having connection pads disposed thereon and an inactive surface; a first encapsulant encapsulating at least portions of the first interconnection member and the first semiconductor chip; a second interconnection member disposed on the first interconnection member and the first semiconductor chip; a second semiconductor chip disposed on the first encapsulant and having an active surface having connection pads disposed thereon; and a second encapsulant encapsulating at least portions of the second semiconductor chip. The first interconnection member and the second interconnection member include, respectively, redistribution layers electrically connected to the connection pads of the first semiconductor chip, and the connection pads of the second semiconductor chip are electrically connected to the redistribution layer of the first interconnection member by wires.

公开(公告)号：US10141288B2

公开(公告)日：2018-11-27

申请号：US14815388

申请日：2015-07-31

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Cheng-Hsien Hsieh ,  Hsien-Wei Chen ,  Chi-Hsi Wu ,  Chen-Hua Yu ,  Der-Chyang Yeh ,  Wei-Cheng Wu

IPC分类号： H01L23/02 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L25/10 ,  H01L25/00 ,  H01L23/00 ,  H01L21/56

摘要： Package structures and methods of forming them are described. In an embodiment, a package structure includes an integrated circuit die embedded in an encapsulant and a redistribution structure on the encapsulant. The redistribution structure includes a metallization layer distal from the encapsulant and the integrated circuit die, and a dielectric layer distal from the encapsulant and the integrated circuit die and on the metallization layer. The package structure also includes a first under metallization structure on the dielectric layer and a Surface Mount Device and/or Integrated Passive Device (“SMD/IPD”) attached to the first under metallization structure. The first under metallization structure includes first through fourth extending portions extending through first through fourth openings of the dielectric layer to first through fourth patterns of the metallization layer, respectively. The first opening, the second opening, the third opening, and the fourth opening are physically separated from each other.

公开(公告)号：US10134947B2

公开(公告)日：2018-11-20

申请号：US15872202

申请日：2018-01-16

申请人： EPISTAR CORPORATION

发明人： Chia Chen Tsai ,  Chen Ou ,  Chi Ling Lee ,  Chi Shiang Hsu

IPC分类号： H01L23/02 ,  H01L33/00 ,  H01L33/62 ,  H01L33/02 ,  H01L33/22 ,  H01L33/20 ,  H01L21/784 ,  H01L21/78

摘要： A compound semiconductor device includes a substrate, including a top surface, a bottom surface, a side surface connecting the top surface and the bottom surface; and a semiconductor stack formed on the top surface, wherein the side surface includes a first deteriorated surface, a second deteriorated surface, a first crack surface between the first and second deteriorated surfaces, a second crack surface between the first deteriorated surface and the top surface, and a third crack surface between the second deteriorated surface and the bottom surface, wherein a convex region or a concave region is formed by the first deteriorated surface, the first crack surface and the second crack surface, or the second deteriorated surface, the first crack surface and the third crack surface; and wherein the second crack surface or the third crack surface is substantially perpendicular to the top surface or the bottom surface.

公开(公告)号：US10128221B2

公开(公告)日：2018-11-13

申请号：US14598679

申请日：2015-01-16

申请人： Silergy Semiconductor Technology (Hangzhou) Ltd.

发明人： Xiaochun Tan ,  Jiaming Ye

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L23/02 ,  H01L23/34 ,  H01L25/16 ,  H01L25/00 ,  H01L23/495 ,  H01L21/48 ,  H01L23/00 ,  H01L23/498 ,  H01L23/31

摘要： A package assembly and a method for manufacturing the same are disclosed. The package assembly includes a leadframe having at least two groups of leads and a plurality of electronic devices arranged in at least two levels. Each group of leads is electrically coupled to a respective level of electronic devices. The package assembly further includes an interconnect for coupling one or more leads of one group of leads to one or more leads of another group of leads. The package assembly results in increased packaging density, less usage of bonding wires in the package assembly, improves reliability, and prevents possible interference.

公开(公告)号：US10128205B2

公开(公告)日：2018-11-13

申请号：US14199545

申请日：2014-03-06

申请人： Intel Corporation

发明人： Thorsten Meyer ,  Sven Albers

IPC分类号： H01L23/02 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H01L25/10 ,  G06F1/16 ,  H01L23/522 ,  H01L25/065 ,  H01L25/00 ,  H01L23/50

摘要： Embodiments of the present disclosure describe integrated circuit (IC) package assemblies and methods of fabricating IC package assemblies. These embodiments include dies embedded in embedding substrates to provide larger pitch interconnects to facilitate coupling to substrates or circuit boards through flip chip techniques. The embedding substrates may contain conductive pathways for coupling die contacts to larger pitch contacts located on the embedding substrate. By embedding the dies in the embedding substrates, dies having smaller pitch contacts can be used in package assemblies with larger pitch components without the need for silicon interposers and without having to utilize more stringent pick and place operations. Other embodiments may be described and/or claimed.

公开(公告)号：US10121769B2

公开(公告)日：2018-11-06

申请号：US15437766

申请日：2017-02-21

申请人： Samsung Electro-Mechanics, Co., Ltd.

发明人： Dae Hyun Park ,  Eun Jung Jo ,  Sung Won Jeong ,  Han Kim ,  Mi Ja Han

IPC分类号： H01L23/02 ,  H01L25/065 ,  H01L23/00 ,  H01L23/31

摘要： A fan-out semiconductor package includes: a first interconnection member having a through-hole; a first semiconductor chip disposed in the through-hole and having an active surface having connection pads disposed thereon and an inactive surface; a first encapsulant encapsulating at least portions of the first interconnection member and the first semiconductor chip; a second interconnection member disposed on the first interconnection member and the first semiconductor chip; a second semiconductor chip disposed on the first encapsulant and having an active surface having connection pads disposed thereon; and a second encapsulant encapsulating at least portions of the second semiconductor chip. The first interconnection member and the second interconnection member include, respectively, redistribution layers electrically connected to the connection pads of the first semiconductor chip, and the connection pads of the second semiconductor chip are electrically connected to the redistribution layer of the first interconnection member by wires.

公开(公告)号：US20180308775A1

公开(公告)日：2018-10-25

申请号：US15908402

申请日：2018-02-28

申请人： FUJI ELECTRIC CO., LTD.

发明人： Tomofumi OOSE

IPC分类号： H01L23/02 ,  H01L23/498 ,  H01L23/538 ,  H01L23/535

CPC分类号： H01L23/02 ,  H01L23/49811 ,  H01L23/535 ,  H01L23/5385 ,  H01L23/5387

摘要： In a semiconductor device, when a printed circuit board is pressed against a bottom part of a case with an adhesive interposed therebetween, the back surface of the printed circuit board is supported by projections formed on the bottom part. Since the gap between the printed circuit board and the bottom part is maintained to have substantially the same height as the projections, the adhesive pressed by the printed circuit board does not spread excessively. At each edge of the printed circuit board in the long-side direction, the end of the adhesive is aligned with or extends slightly beyond the edge. In the short-side direction, the adhesive extends beyond each edge of the printed circuit board, but does not extend over the front surface of the printed circuit board, internal connection terminals, or the front surface of a ceramic circuit board.

公开(公告)号：US20180286816A1

公开(公告)日：2018-10-04

申请号：US15934829

申请日：2018-03-23

申请人： TAIYO YUDEN CO., LTD.

发明人： Kenzo KITAZAKI ,  Takehiko KAI ,  Masaya SHIMAMURA ,  Mikio AOKI ,  Jin MIKATA ,  Taiji ITO

IPC分类号： H01L23/552 ,  H01L23/28 ,  H01L23/02

摘要： To provide an electronic component module capable of forming a shielding film in a state of an assembly substrate and enhancing productivity. An electronic component module includes: a substrate including a conductive pattern; an electronic component provided to the substrate; a sealing portion covering the electronic component and the substrate, the sealing portion having an upper surface and a side surface, the upper surface and the side surface forming an edge portion; a contact portion provided to the substrate, the contact portion being configured to be electrically connected with the conductive pattern, the contact portion having a vertical surface continuous with the side surface of the sealing portion and a horizontal surface continuous with the vertical surface; and a shielding film covering the upper surface and the side surface of the sealing portion and the contact portion.

公开(公告)号：US10068828B2

公开(公告)日：2018-09-04

申请号：US15478252

申请日：2017-04-04

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Min-Young Choi ,  Young-Rok Oh ,  Hwi-Jong Yoo ,  Il-Soo Kim ,  Joo-Young Kim ,  Ki-Taek Lee ,  Eun-Ji Yu

IPC分类号： H01L23/02 ,  H01L23/367 ,  H01L23/00 ,  H01L23/498 ,  H01L25/065

摘要： A semiconductor storage device includes a circuit substrate. The circuit substrate includes a main body and a connection tab connected to a side of the main body. The a main body includes a first chip mounting region and a second chip mounting region. A first semiconductor chip of a first type is mounted on the first chip mounting region. A second semiconductor chip of a second type is mounted on the second chip mounting region. The first type of the first semiconductor chip is different from the second type of the second semiconductor chip. The circuit substrate further includes a first thermal via in the connection tab and comprising a conductive material.

公开(公告)号：US10054609B2

公开(公告)日：2018-08-21

申请号：US15549421

申请日：2016-02-01

申请人： DENSO CORPORATION

发明人： Toshihiko Takahata ,  Eiichi Taketani

IPC分类号： H01L23/48 ,  G01P15/08 ,  H01L29/84 ,  H01L23/02

CPC分类号： G01P15/08 ,  B81B2201/0235 ,  B81B2207/095 ,  B81C1/00301 ,  B81C2203/0109 ,  G01P15/0802 ,  G01P2015/0828 ,  H01L23/02 ,  H01L29/84

摘要： A method for manufacturing a semiconductor device includes: preparing a first substrate; forming a metal film having a Ti layer as the most outermost surface on one surface of the first substrate a metal film having a Ti layer as the outermost surface; patterning the metal film to form a first pad portion; preparing a second substrate; forming on one surface of the second substrate a metal film having a Ti layer as the outermost surface; patterning the metal film to form a second pad portion; vacuum annealing the first substrate and the second substrate to remove an oxide film formed on the Ti layer in the first pad portion and the second pad portion; and bonding the first pad portion and the second pad portion together.