公开(公告)号：US20190392337A1

公开(公告)日：2019-12-26

申请号：US16445316

申请日：2019-06-19

申请人： equal1.labs Inc.

发明人： Dirk Robert Walter Leipold ,  George Adrian Maxim ,  Michael Albert Asker

IPC分类号： G06N10/00 ,  H01L29/15 ,  H01L29/12 ,  H01L39/22 ,  B82Y15/00 ,  B82Y10/00

摘要： Novel and useful quantum structures having a continuous well with control gates that control a local depletion region to form quantum dots. Local depleted well tunneling is used to control quantum operations to implement quantum computing circuits. Qubits are realized by modulating gate potential to control tunneling through local depleted region between two or more sections of the well. Complex structures with a higher number of qdots per continuous well and a larger number of wells are fabricated. Both planar and 3D FinFET semiconductor processes are used to build well to gate and well to well tunneling quantum structures. Combining a number of elementary quantum structure, a quantum computing machine is realized. An interface device provides an interface between classic circuitry and quantum circuitry by permitting tunneling of a single quantum particle from the classic side to the quantum side of the device. Detection interface devices detect the presence or absence of a particle destructively or nondestructively.

公开(公告)号：US10510876B2

公开(公告)日：2019-12-17

申请号：US15834610

申请日：2017-12-07

申请人： Anatoly Feygenson

发明人： Anatoly Feygenson

IPC分类号： H01L29/772 ,  H01L29/36 ,  H01L21/02 ,  H01L29/778 ,  H01L29/12 ,  H01L29/15 ,  H01L21/225 ,  H01L21/67 ,  H01L29/8605 ,  H01L21/3215 ,  H01L21/203 ,  H01L29/66 ,  H01L29/08 ,  H01L29/16

摘要： A novel doping technology for semiconductor wafers has been developed, referred to as a “quantum doping” process that permits the deposition of only a fixed, controlled number of atoms in the form of a monolayer in a substitutional condition where only unterminated surface bonds react with the dopant, thus depositing only a number of atoms equal to the atomic surface density of the substrate material. This technique results in providing a “quantized” set of possible dopant concentration values that depend only on the additional number of layers of substrate material formed over the single layer of dopant atoms.

公开(公告)号：US20190363181A1

公开(公告)日：2019-11-28

申请号：US16097730

申请日：2016-06-29

申请人： Intel Corporation

发明人： Ravi Pillarisetty ,  Van H. Le ,  Jeanette M. Roberts ,  James S. Clarke ,  Zachary R. Yoscovits ,  David J. Michalak

IPC分类号： H01L29/66 ,  H01L29/06 ,  H01L29/12 ,  H01L29/786

摘要： Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack including a quantum well layer, a doped layer, and a barrier layer disposed between the doped layer and the quantum well layer; and gates disposed above the quantum well stack. The doped layer may include a first material and a dopant, the first material may have a first diffusivity of the dopant, the barrier layer may include a second material having a second diffusivity of the dopant, and the second diffusivity may be less than the first diffusivity.

公开(公告)号：US10431677B2

公开(公告)日：2019-10-01

申请号：US15561800

申请日：2016-02-08

申请人： ROHM CO., LTD.

发明人： Yuki Nakano

IPC分类号： H01L29/78 ,  H01L29/06 ,  H01L29/12 ,  H01L29/423 ,  H01L29/49 ,  H01L29/417 ,  H01L29/10 ,  H01L29/16 ,  H01L29/20

摘要： The semiconductor device of the present invention includes a semiconductor layer which includes an active portion and a gate finger portion, an MIS transistor which is formed at the active portion and includes a gate trench as well as a source region, a channel region and a drain region sequentially along a side surface of the gate trench, a plurality of first gate finger trenches arranged by an extended portion of the gate trench at the gate finger portion, a gate electrode embedded each in the gate trench and the first gate finger trench, a second conductive-type first bottom-portion impurity region formed at least at a bottom portion of the first gate finger trench, a gate finger which crosses the plurality of first gate finger trenches and is electrically connected to the gate electrode, and a second conductive-type electric field relaxation region which is formed more deeply than the bottom portion of the first gate finger trench between the mutually adjacent first gate finger trenches.

公开(公告)号：US20190296131A1

公开(公告)日：2019-09-26

申请号：US16424457

申请日：2019-05-28

申请人： Matthew H. Kim

发明人： Matthew H. Kim

IPC分类号： H01L29/737 ,  H01L29/10 ,  H01L29/66 ,  H01L29/20 ,  H01L29/267 ,  H01L33/00 ,  H01L29/08 ,  H01L29/12 ,  H01L29/165

摘要： The methods of manufacture of GeSiSn heterojunction bipolar transistors, which include light emitting transistors and transistor lasers and photo-transistors and their related structures are described herein. Other embodiments are also disclosed herein.

公开(公告)号：US10418384B2

公开(公告)日：2019-09-17

申请号：US15957318

申请日：2018-04-19

申请人： Semiconductor Energy Laboratory Co., Ltd.

发明人： Shunpei Yamazaki ,  Toshinari Sasaki ,  Junichiro Sakata ,  Masashi Tsubuku

IPC分类号： H01L29/10 ,  H01L29/12 ,  H01L27/12 ,  H01L29/45 ,  H01L29/786 ,  H01L29/24 ,  H01L29/423 ,  H01L29/49 ,  H01L27/32

摘要： It is an object to manufacture a highly reliable display device using a thin film transistor having favorable electric characteristics and high reliability as a switching element. In a bottom gate thin film transistor including an amorphous oxide semiconductor, an oxide conductive layer having a crystal region is formed between an oxide semiconductor layer which has been dehydrated or dehydrogenated by heat treatment and each of a source electrode layer and a drain electrode layer which are formed using a metal material. Accordingly, contact resistance between the oxide semiconductor layer and each of the source electrode layer and the drain electrode layer can be reduced; thus, a thin film transistor having favorable electric characteristics and a highly reliable display device using the thin film transistor can be provided.

公开(公告)号：US10403762B2

公开(公告)日：2019-09-03

申请号：US15597237

申请日：2017-05-17

申请人： Semiconductor Energy Laboratory Co., Ltd.

发明人： Shunpei Yamazaki ,  Hideomi Suzawa

IPC分类号： H01L29/12 ,  H01L29/786 ,  H01L29/49 ,  H01L29/51

摘要： A transistor that is to be provided has such a structure that a source electrode layer and a drain electrode layer between which a channel formation region is sandwiched has regions projecting in a channel length direction at lower end portions, and an insulating layer is provided, in addition to a gate insulating layer, between the source and drain electrode layers and a gate electrode layer. In the transistor, the width of the source and drain electrode layers is smaller than that of an oxide semiconductor layer in the channel width direction, so that an area where the gate electrode layer overlaps with the source and drain electrode layers can be made small. Further, the source and drain electrode layers have regions projecting in the channel length direction at lower end portions.

公开(公告)号：US10403727B2

公开(公告)日：2019-09-03

申请号：US16129554

申请日：2018-09-12

申请人： TOYODA GOSEI CO., LTD.

发明人： Tsutomu Ina ,  Yukihisa Ueno ,  Tohru Oka

IPC分类号： H01L29/78 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423 ,  H01L29/06 ,  H01L29/12 ,  H01L29/739 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/16 ,  H01L29/20

摘要： To provide a technique for alleviating electric field concentration at an end portion and the vicinity of the end portion of the bottom surface of a trench. In a non-active region, a semiconductor device comprises: an outer trench penetrating a third semiconductor layer and a second semiconductor layer to reach a first semiconductor layer, and surrounding an active region; a second insulating film covering the surface of the outer trench; a conductor formed in the outer trench covered by the second insulating film and electrically insulated from a control electrode and a contact electrode; and an outer electrode located outside the outer trench, contacting the second semiconductor layer, and being electrically connected to the contact electrode.

公开(公告)号：US10403628B2

公开(公告)日：2019-09-03

申请号：US14581472

申请日：2014-12-23

申请人： International Business Machines Corporation

发明人： Ravikumar Ramachandran ,  Reinaldo Ariel Vega

IPC分类号： H01L29/66 ,  H01L29/78 ,  H01L27/108 ,  H01L29/10 ,  H01L29/165 ,  H01L29/12

摘要： Embodiments of the present invention provide improved methods and structures for fabrication of capacitor-less DRAM devices, sometimes referred to as ZRAM devices. A channel is formed in a fin-type field effect transistor (finFET) that is comprised of a finned channel portion and a convex channel portion. The finned channel portion may be comprised of a first semiconductor material and the convex channel portion may be comprised of a second, different semiconductor material. In embodiments, a metal gate is disposed around the elongated surface of the channel region, but is not disposed on the short surface of the channel region. A first spacer is disposed adjacent to the gate and in direct physical contact with the short surface of the channel region, and a second spacer is disposed adjacent to the first spacer.

公开(公告)号：US10396213B2

公开(公告)日：2019-08-27

申请号：US15853984

申请日：2017-12-26

申请人： Chunghwa Picture Tubes, LTD.

发明人： Chin-Hai Huang ,  Ya-Ju Lu ,  Shang-Jung Yang ,  Yen-Yu Huang

IPC分类号： H01L29/10 ,  H01L29/12 ,  H01L29/04 ,  H01L27/14 ,  H01L29/15 ,  H01L29/786 ,  H01L27/12 ,  H01L29/49 ,  H01L29/417

摘要： An active device array substrate includes a substrate, first and second active devices, a gate insulation layer and an insulation barrier layer. The first and second active devices respectively includes first and second gate electrodes, first and second semiconductor blocks, first and second source electrodes, and first and second drain electrodes. A film layer of the second source electrode and the second drain electrode is the same with that of the first source electrode or the first drain electrode. The gate insulation layer is located between the first gate electrode and the first semiconductor block and between the second gate electrode and the second semiconductor block. The insulation barrier layer is disposed on the gate insulation layer, and covers the first semiconductor block. The insulation barrier layer has a first through hole for one of the first source electrode and the first drain electrode contacting the first semiconductor block.