Photomask and method for detecting violations in a mask pattern file using a manufacturing rule
    1.
    发明授权
    Photomask and method for detecting violations in a mask pattern file using a manufacturing rule 失效
    用于使用制造规则检测掩模图案文件中的违规的光掩模和方法

    公开(公告)号:US06899981B1

    公开(公告)日:2005-05-31

    申请号:US10301195

    申请日:2002-11-21

    IPC分类号: G03F1/14 G03F9/00

    CPC分类号: G03F1/36 G03F1/70

    摘要: A photomask and method for detecting failures in a mask pattern file using a manufacturing rule are disclosed. The method includes calculating a manufacturing rule based on a design parameter associated with a manufacturing process and measuring a dimension of a non-linear feature in a mask pattern file. A rule violation is identified in the mask pattern file if the measured dimension is less than the calculated manufacturing rule.

    摘要翻译: 公开了一种使用制造规则检测掩模图案文件中的故障的光掩模和方法。 该方法包括基于与制造过程相关联的设计参数来计算制造规则并测量掩模图案文件中的非线性特征的尺寸。 如果测量尺寸小于计算的制造规则,则在掩模图案文件中识别规则违规。

    System and method for generating a mask layout file to reduce power supply voltage fluctuations in an integrated circuit
    2.
    发明授权
    System and method for generating a mask layout file to reduce power supply voltage fluctuations in an integrated circuit 失效
    用于生成掩模布局文件以减少集成电路中的电源电压波动的系统和方法

    公开(公告)号:US06877144B1

    公开(公告)日:2005-04-05

    申请号:US10378537

    申请日:2003-03-03

    IPC分类号: G06F17/50

    CPC分类号: G06F17/5068

    摘要: A system and method for generating a mask layout file to reduce power supply voltage fluctuations in an integrated circuit are disclosed. The method includes analyzing a pattern in a mask layout file to identify a region in the pattern to add one or more decoupling capacitors. Once the region is identified, a feature located in the identified region is moved based on a design rule from a first position to a second position in the mask layout file to create a space in the identified region. The decoupling capacitors are automatically placed in the space in the identified region.

    摘要翻译: 公开了一种用于产生掩模布局文件以减少集成电路中的电源电压波动的系统和方法。 该方法包括分析掩模布局文件中的图案以识别图案中的区域以添加一个或多个去耦电容器。 一旦区域被识别,位于识别区域中的特征将基于设计规则从掩模布局文件中的第一位置移动到第二位置,以在识别的区域中创建空间。 去耦电容器自动放置在识别区域的空间中。

    Damage resistant photomask construction
    3.
    发明授权
    Damage resistant photomask construction 失效
    耐损伤的光掩模结构

    公开(公告)号:US06841309B1

    公开(公告)日:2005-01-11

    申请号:US10044076

    申请日:2002-01-11

    IPC分类号: G03F1/14 G03F9/00

    CPC分类号: G03F1/48

    摘要: A method for fabricating a damage resistant photomask includes forming a photomask pattern on a substrate and forming a transparent, protective coating on the photomask pattern. The protective coating may be an electrical insulator (e.g., spin-on glass). In addition, an antireflective layer may be applied to the protective coating. A pellicle may also be attached over the protective coating. The protective coating may prevent electrostatic energy from forming on or arcing between features on the photomask pattern and damaging the features. The protective layer may also prevent the photomask pattern from being damaged by or reacting with other substances, such as cleaning solutions.

    摘要翻译: 制造耐损伤光掩模的方法包括在基片上形成光掩模图案,并在光掩模图案上形成透明保护涂层。 保护涂层可以是电绝缘体(例如旋涂玻璃)。 此外,可以将抗反射层施加到保护涂层。 防护薄膜也可以附着在保护涂层上。 保护涂层可以防止静电能量在光掩模图案上的特征之间形成或电弧,并损坏特征。 保护层也可以防止光掩模图案被其他物质如清洁溶液损坏或与其反应。

    System and method for correcting design rule violations in a mask layout file
    4.
    发明申请
    System and method for correcting design rule violations in a mask layout file 审中-公开
    用于校正掩码布局文件中设计规则违规的系统和方法

    公开(公告)号:US20020144230A1

    公开(公告)日:2002-10-03

    申请号:US10159566

    申请日:2002-05-31

    发明人: Dan Rittman

    IPC分类号: G06F017/50

    CPC分类号: G06F17/5081 G03F1/36

    摘要: A system and method for correcting design rule violations in a mask layout file are disclosed. The method includes comparing a feature dimension in a mask layout file with a design rule in a technology file. If the feature dimension is less than the design rule, a design rule violation is identified and automatically corrected in the mask layout file.

    摘要翻译: 公开了一种用于校正掩模布局文件中的设计规则违规的系统和方法。 该方法包括将掩模布局文件中的特征维度与技术文件中的设计规则进行比较。 如果特征尺寸小于设计规则,则会在掩模布局文件中识别设计规则违规并自动更正。

    Varible surface hot plate for improved bake uniformity of substrates
    5.
    发明申请
    Varible surface hot plate for improved bake uniformity of substrates 失效
    可变表面热板,用于提高基材的烘烤均匀性

    公开(公告)号:US20020086248A1

    公开(公告)日:2002-07-04

    申请号:US09990791

    申请日:2001-11-16

    摘要: A system, method and apparatus are described for improving critical dimension uniformity in baked substrates. The system, method and apparatus provide for varying the distance between a substrate to be baked and the surface of a hot plate such that an approximately uniform temperature is obtained in the substrate during baking. In one embodiment, the substrate is positioned on a hot plate having a recess generally centered on its top side. The differences in distance between the edges of the substrates contacting the hot plate and the distance between the center region of the substrate and the bottom of the recess enable a generally uniform temperature to be obtained in the substrate.

    摘要翻译: 描述了一种系统,方法和装置,用于改善焙烧基材中的临界尺寸均匀性。 该系统,方法和装置提供了改变要烘烤的基材和热板的表面之间的距离,使得在烘烤期间在基材中获得大致均匀的温度。 在一个实施例中,基板定位在热板上,该热板具有通常以其顶侧为中心的凹槽。 接触热板的基板的边缘与基板的中心区域与凹部的底部之间的距离的差异使得能够在基板中获得大致均匀的温度。

    Photomask for reducing power supply voltage fluctuations in an integrated circuit and integrated circuit manufactured with the same
    7.
    发明授权
    Photomask for reducing power supply voltage fluctuations in an integrated circuit and integrated circuit manufactured with the same 失效
    用于降低集成电路中的电源电压波动的光掩模和与其制造的集成电路

    公开(公告)号:US06904582B1

    公开(公告)日:2005-06-07

    申请号:US10378452

    申请日:2003-03-03

    IPC分类号: G06F17/50

    CPC分类号: G06F17/5068

    摘要: A photomask for reducing power supply voltage fluctuations in an integrated circuit and integrated circuit manufactured by the same are disclosed. The photomask includes a substrate and a patterned layer formed on at least a portion of the substrate. The patterned layer may be formed using a mask pattern file created by analyzing a pattern in a mask layout file to identify a region in the pattern to add one or more decoupling capacitors. Once the region is identified, a feature located in the identified region is moved based on a design rule from a first position to a second position in the mask layout file to create a space in the identified region. The decoupling capacitors are placed in the space in the identified region.

    摘要翻译: 公开了一种用于降低集成电路中的电源电压波动的光掩模和由其制造的集成电路。 光掩模包括基板和形成在基板的至少一部分上的图案层。 图案化层可以使用通过分析掩模布局文件中的图案而产生的掩模图案文件来形成,以识别图案中的区域以添加一个或多个去耦电容器。 一旦区域被识别,位于识别区域中的特征将基于设计规则从掩模布局文件中的第一位置移动到第二位置,以在识别的区域中创建空间。 去耦电容器放置在识别区域的空间中。

    Photomask and integrated circuit manufactured by automatically correcting design rule violations in a mask layout file
    8.
    发明申请
    Photomask and integrated circuit manufactured by automatically correcting design rule violations in a mask layout file 失效
    光掩模和集成电路通过自动校正掩模布局文件中的设计规则违规而制造

    公开(公告)号:US20020152453A1

    公开(公告)日:2002-10-17

    申请号:US10161527

    申请日:2002-06-03

    发明人: Dan Rittman

    IPC分类号: G06F017/50

    CPC分类号: G06F17/5081 G03F1/36

    摘要: A photomask and method for eliminating design rule violations from the photomask are disclosed. A photomask includes a substrate and a patterned layer formed on at least a portion of the substrate. The patterned layer may be formed using a mask pattern file created by comparing a feature dimension in a mask layout file with a design rule in a technology file, identifying a design rule violation if the feature dimension is less than the design rule and automatically correcting the identified design rule violation in the mask layout file.

    摘要翻译: 公开了一种用于从光掩模中消除违反设计规则的光掩模和方法。 光掩模包括衬底和形成在衬底的至少一部分上的图案层。 图案化层可以使用通过将掩模布局文件中的特征尺寸与技术文件中的设计规则进行比较而创建的掩模图案文件来形成,如果特征尺寸小于设计规则,则识别设计规则违反,并且自动校正 在面具布局文件中识别设计规则违规。

    Variable surface hot plate for improved bake uniformity of substrates
    9.
    发明申请
    Variable surface hot plate for improved bake uniformity of substrates 失效
    可变表面热板,用于提高基材的烘烤均匀性

    公开(公告)号:US20020092843A1

    公开(公告)日:2002-07-18

    申请号:US10073711

    申请日:2002-02-11

    IPC分类号: F27D011/00 H05B003/68

    摘要: A system, method and apparatus are described for improving critical dimension uniformity in baked substrates. The system, method and apparatus provide for varying the distance between a substrate to be baked and the surface of a hot plate such that an approximately uniform temperature is obtained in the substrate during baking. In one embodiment, the substrate is positioned on a hot plate having a recess generally centered on its top side. The differences in distance between the edges of the substrates contacting the hot plate and the distance between the center region of the substrate and the bottom of the recess enable a generally uniform temperature to be obtained in the substrate.

    摘要翻译: 描述了一种系统,方法和装置,用于改善焙烧基材中的临界尺寸均匀性。 该系统,方法和装置提供了改变要烘烤的基材和热板的表面之间的距离,使得在烘烤期间在基材中获得大致均匀的温度。 在一个实施例中,基板定位在热板上,该热板具有通常以其顶侧为中心的凹槽。 接触热板的基板的边缘与基板的中心区域与凹部的底部之间的距离的差异使得能够在基板中获得大致均匀的温度。

    Test wafer and method for investigating electrostatic discharge induced wafer defects
    10.
    发明申请
    Test wafer and method for investigating electrostatic discharge induced wafer defects 失效
    测试晶片和调查静电放电诱发晶片缺陷的方法

    公开(公告)号:US20020076840A1

    公开(公告)日:2002-06-20

    申请号:US10071167

    申请日:2002-02-08

    发明人: Andreas Englisch

    IPC分类号: H01L021/66

    CPC分类号: H01L22/34 G03F1/40 G03F1/84

    摘要: A test wafer and method for investigating electrostatic discharge induced wafer defects are disclosed. The test wafer includes an electrostatic discharge (ESD) sensitive risk scale geometry, formed thereon. After exposure to a semiconductor manufacturing procedure, the test wafer may be analyzed by using the ESD risk scale geometry to identify and evaluate severity of any ESD effects associated with the semiconductor manufacturing procedure.

    摘要翻译: 公开了用于研究静电放电感应晶片缺陷的测试晶片和方法。 测试晶片包括在其上形成的静电放电(ESD)敏感的风险标度几何形状。 在暴露于半导体制造程序之后,可以通过使用ESD风险等级几何来分析测试晶片,以识别和评估与半导体制造过程相关的任何ESD效应的严重性。