公开(公告)号：US08319266B1

公开(公告)日：2012-11-27

申请号：US11008240

申请日：2004-12-10

Applicant: Hiroyuki Kinoshita ,  Angela Hui ,  Hsiao-Han Thio ,  Kuo-Tung Chang ,  Minh Van Ngo ,  Hiroyuki Ogawa

Inventor： Hiroyuki Kinoshita ,  Angela Hui ,  Hsiao-Han Thio ,  Kuo-Tung Chang ,  Minh Van Ngo ,  Hiroyuki Ogawa

IPC: H01L29/788

CPC classification number: H01L21/0217 ,  H01L21/28273 ,  H01L29/66825 ,  H01L29/7881

Abstract: A memory device and a method of making the memory device are provided. A first dielectric layer is formed on a substrate, a floating gate is formed on the first dielectric layer, a second dielectric layer is formed on the floating gate, a control gate is formed on the second dielectric layer, and at least one film, including a conformal film, is formed over a surface of the memory device.

Abstract translation: 提供存储器件和制造存储器件的方法。 在基板上形成第一电介质层，在第一电介质层上形成浮栅，在浮栅上形成第二电介质层，在第二电介质层上形成控制栅，还包括至少一层， 保形膜形成在存储器件的表面上。

公开(公告)号：US07599228B1

公开(公告)日：2009-10-06

申请号：US10976760

申请日：2004-11-01

Applicant: Qiang Lu ,  Kuo-Tung Chang ,  Kazuhiro Mizutani ,  Sung-Chul Lee ,  Sheung-Hee Park ,  Ming-Sang Kwan

Inventor： Qiang Lu ,  Kuo-Tung Chang ,  Kazuhiro Mizutani ,  Sung-Chul Lee ,  Sheung-Hee Park ,  Ming-Sang Kwan

IPC: G11C16/04

CPC classification number: G11C16/3404

Abstract: A memory device is provided including circuitry for correcting an over-erased memory cell in the memory device. The memory device may include a substrate. A control gate and a floating gate may be formed over the substrate. The memory device may include a source region and a drain region. A first resistive element may be coupled between the source region and the control gate.

Abstract translation: 提供了一种存储器件，其包括用于校正存储器件中的擦除过的存储器单元的电路。 存储器件可以包括衬底。 可以在衬底上形成控制栅极和浮置栅极。 存储器件可以包括源极区域和漏极区域。 第一电阻元件可以耦合在源极区域和控制栅极之间。

公开(公告)号：US20080049516A1

公开(公告)日：2008-02-28

申请号：US11931992

申请日：2007-10-31

Applicant: Aaron LEE ,  Hounien CHEN ,  Sachit CHANDRA ,  Nancy LEONG ,  Guowei WANG

Inventor： Aaron LEE ,  Hounien CHEN ,  Sachit CHANDRA ,  Nancy LEONG ,  Guowei WANG

IPC: G11C11/34

CPC classification number: G11C16/0475 ,  G11C16/3454 ,  G11C16/3459

Abstract: A method is provided for programming a nonvolatile memory device including an array of memory cells, where each memory cell including a substrate, a control gate, a charge storage element, a source region and a drain region. The method includes receiving a programming window that identifies a plurality of memory cells in the array. A first group of memory cells to be programmed is identified from the plurality of memory cells in the programming window. The first group of memory cells is programmed and a programming state of the first group of memory cells is verified.

Abstract translation: 提供了一种用于对包括存储器单元阵列的非易失性存储器件进行编程的方法，其中每个存储器单元包括衬底，控制栅极，电荷存储元件，源极区域和漏极区域。 该方法包括接收标识阵列中的多个存储单元的编程窗口。 在编程窗口中从多个存储器单元识别要编程的第一组存储器单元。 第一组存储器单元被编程，并且验证第一组存储器单元的编程状态。

公开(公告)号：US07167398B1

公开(公告)日：2007-01-23

申请号：US11062641

申请日：2005-02-23

Applicant: Zhizheng Liu ,  Satoshi Torii ,  Mark Randolph ,  Yi He

Inventor： Zhizheng Liu ,  Satoshi Torii ,  Mark Randolph ,  Yi He

IPC: G11C11/34 ,  G11C16/04

CPC classification number: G11C16/0475 ,  G11C16/14 ,  H01L29/66833 ,  H01L29/7923

Abstract: A method erases a memory cell of a semiconductor device that includes a group of memory cells. Each memory cell includes a group of storage regions. The method includes determining that each storage region of the group of storage regions of a first memory cell is to be erased and erasing the group of storage regions of the first memory cell via a single hot hole injection process.

Abstract translation: 一种方法擦除包括一组存储单元的半导体器件的存储单元。 每个存储单元包括一组存储区域。 该方法包括：通过单个热孔注入处理确定要擦除第一存储器单元组的存储区域的每个存储区域并擦除第一存储单元的存储区域组。

公开(公告)号：US07402868B2

公开(公告)日：2008-07-22

申请号：US10976816

申请日：2004-11-01

Applicant: Ihsan Jahed Djomehri ,  Mark Randolph ,  Yi He ,  Wei Zheng

Inventor： Ihsan Jahed Djomehri ,  Mark Randolph ,  Yi He ,  Wei Zheng

IPC: H01L23/62

CPC classification number: H01L27/115 ,  H01L27/0288

Abstract: A semiconductor memory device includes a group of word lines and a structure that is configured to dissipate current from the group of word lines during fabrication of the semiconductor memory device.

Abstract translation: 半导体存储器件包括一组字线和被配置成在制造半导体存储器件期间消散来自字线组的电流的结构。

公开(公告)号：US20080142889A1

公开(公告)日：2008-06-19

申请号：US11612265

申请日：2006-12-18

Applicant: Wei ZHENG ,  Jean YANG ,  Mark RANDOLPH ,  Ming KWAN ,  Yi HE ,  Zhizheng LIU ,  Meng DING

Inventor： Wei ZHENG ,  Jean YANG ,  Mark RANDOLPH ,  Ming KWAN ,  Yi HE ,  Zhizheng LIU ,  Meng DING

IPC: H01L23/62 ,  H01L29/76 ,  H01L21/336

CPC classification number: H01L27/105 ,  H01L27/11526 ,  H01L27/11531

Abstract: A semiconductor device includes a substrate and a memory cell formed on the substrate. The memory cell includes a word line. The semiconductor device also includes a protection area formed in the substrate, a conductive structure configured to extend the word line to the protection area, and a contact configured to short the word line and the protection area.

Abstract translation: 半导体器件包括衬底和形成在衬底上的存储单元。 存储单元包括字线。 半导体器件还包括形成在衬底中的保护区域，被配置为将字线延伸到保护区域的导电结构以及被配置为使字线和保护区域短路的触点。

公开(公告)号：US07079424B1

公开(公告)日：2006-07-18

申请号：US10945914

申请日：2004-09-22

Applicant: Sungchul Lee ,  Sheunghee Park ,  Yue-Song He ,  Ming Sang Kwan

Inventor： Sungchul Lee ,  Sheunghee Park ,  Yue-Song He ,  Ming Sang Kwan

IPC: G11C11/34

CPC classification number: G11C16/107 ,  G11C16/16 ,  G11C16/3468

Abstract: A method is provided for erasing a memory cell having a substrate, a control gate, a floating gate, a source region and a drain region. The method includes pre-programming the memory cell to raise a threshold voltage of the memory cell to a first predetermined level, wherein pre-programming the memory cell does not include a verification process for ensuring that the threshold voltage of the memory cell has been raised to the first predetermined level. The memory cell may be erased to lower the threshold voltage of the memory cell to a second predetermined level.

Abstract translation: 提供一种用于擦除具有衬底，控制栅极，浮置栅极，源极区域和漏极区域的存储器单元的方法。 该方法包括对存储器单元预编程以将存储器单元的阈值电压升高到第一预定电平，其中预编程存储器单元不包括用于确保存储器单元的阈值电压已被提高的验证过程 到第一预定水平。 可以擦除存储器单元以将存储器单元的阈值电压降低到第二预定电平。

公开(公告)号：US20100240210A1

公开(公告)日：2010-09-23

申请号：US12790578

申请日：2010-05-28

Applicant: Wei ZHENG ,  Jean YANG ,  Mark RANDOLPH ,  Ming KWAN ,  Yi HE ,  Zhizheng LIU ,  Meng DING

Inventor： Wei ZHENG ,  Jean YANG ,  Mark RANDOLPH ,  Ming KWAN ,  Yi HE ,  Zhizheng LIU ,  Meng DING

IPC: H01L21/768

CPC classification number: H01L27/105 ,  H01L27/11526 ,  H01L27/11531

Abstract: A semiconductor device includes a substrate and a memory cell formed on the substrate. The memory cell includes a word line. The semiconductor device also includes a protection area formed in the substrate, a conductive structure configured to extend the word line to the protection area, and a contact configured to short the word line and the protection area.

Abstract translation: 半导体器件包括衬底和形成在衬底上的存储单元。 存储单元包括字线。 半导体器件还包括形成在衬底中的保护区域，被配置为将字线延伸到保护区域的导电结构以及被配置为使字线和保护区域短路的触点。