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公开(公告)号：US20240302040A1
公开(公告)日：2024-09-12
申请号：US18432795
申请日：2024-02-05
IPC分类号： F23N1/00
CPC分类号： F23N1/002 , F23N2227/36 , F23N2229/14
摘要： A sensor device for detecting a flame comprises a carbon dioxide sensor for detecting a CO2 concentration, a fuel sensor for detecting the combustion of a fuel, an electrostatic charge variation sensor for detecting electrostatic charge variations generated by the flame, and a control unit. The control unit is configured to acquire a carbon dioxide signal indicative of the concentration of carbon dioxide, a fuel signal indicative of the fuel combustion, and an electrostatic charge variation signal indicative of a difference between the electrostatic charge variations detected by a first and a second electrode of the electrostatic charge variation sensor, determine a quantized signal based on the electrostatic charge variation signal, determine an aggregate datum based on the carbon dioxide signal, the fuel signal and the electrostatic charge variation signal, and generate, based on the aggregate datum, a flame signal indicative of the presence or absence of the flame.
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公开(公告)号：US20230344350A1
公开(公告)日：2023-10-26
申请号：US18297998
申请日：2023-04-10
CPC分类号： H02M3/1582 , H02M1/0016 , H02M3/157
摘要： A buck-boost converter circuit includes a mode selection circuit that asserts a buck enable signal if an input voltage is higher than a lower threshold, and asserts a boost enable signal if the input voltage is lower than an upper threshold. A control circuit asserts a buck PWM signal upon a pulse in a buck clock and de-asserts the buck PWM signal if a buck ramp is higher than a buck control signal, and it keeps the buck PWM signal asserted if the buck enable signal is de-asserted. The control circuit asserts a boost PWM signal upon a pulse in a boost clock and de-asserts the boost PWM signal if a boost ramp is higher than a boost control signal, and it keeps the boost PWM signal de-asserted if the boost enable signal is de-asserted.
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公开(公告)号：US20230291538A1
公开(公告)日：2023-09-14
申请号：US18174183
申请日：2023-02-24
摘要： A method includes providing a reference clock signal having a reference period, providing a sampling clock signal having a sampling clock period shorter than the reference period of the reference clock signal, measuring the first subperiod as a first ratio of the first subperiod to the period of the sampling clock signal, measuring the second subperiod as a second ratio of the second subperiod to the period of the sampling clock signal, detecting a starting edge of a clock signal having a clock period greater than the reference period, producing a reconstructed reference signal based on the first ratio, the second ratio, and the detected starting edge, comparing the clock period of the clock signal with a period of the reconstructed reference signal to obtain a differential signal indicating a difference therebetween, and providing the differential signal to user circuitry for calibrating the clock signal.
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公开(公告)号：US20230288946A1
公开(公告)日：2023-09-14
申请号：US17694182
申请日：2022-03-14
IPC分类号： G05F1/56
CPC分类号： G05F1/56
摘要： In an embodiment, a method includes: providing a voltage setpoint to a voltage converter; generating an output voltage at a voltage rail with the voltage converter based on the voltage setpoint; when the voltage setpoint is transitioning from a first voltage setpoint to a second voltage setpoint that has a lower magnitude than the first voltage setpoint, providing a first constant current to a first node coupled to a control terminal of an output transistor to turn on the output transistor, where the output transistor includes a source terminal coupled to a first terminal of a first resistor, and where a current path of the output transistor is coupled to the voltage rail; and turning off the output transistor after the output voltage reaches the target output voltage corresponding to the second voltage setpoint.
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公开(公告)号：US20230170742A1
公开(公告)日：2023-06-01
申请号：US18154394
申请日：2023-01-13
CPC分类号： H02J50/12 , H04B5/0037 , H04B5/0075
摘要： The present disclosure relates to a device comprising an inductive element and a first capacitive element series connected between a first node and a second node, a first MOS transistor connected between the first node and a third node configured to receive a reference potential, the second node being coupled directly or via a second MOS transistor to the third node, a second capacitive element connected between a fourth node and an interconnection node between the first capacitive element and the inductive element, a current generator configured to provide an AC current to the fourth node, and a switch connected between the fourth node and the third node.
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公开(公告)号：US20230135666A1
公开(公告)日：2023-05-04
申请号：US18062929
申请日：2022-12-07
IPC分类号： H05B45/397 , H05B45/14
摘要： An embodiment LED driver system comprises a power transistor configured to be selectively activated for generating a driving current for an array of LEDs, the power transistor having a first conduction terminal coupled to the array of LEDs and a second conduction terminal coupled to a reference resistor; an operational amplifier having a non-inverting input for receiving a reference voltage, an inverting input coupled to the second conduction terminal of the power transistor, and an output terminal coupled to a first conduction terminal of a transmission gate having a second conduction terminal coupled to a control terminal of the power transistor and a control terminal for receiving an enable signal; and a slew rate control unit configured to control the slew rate of the driving current.
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公开(公告)号：US20220308892A1
公开(公告)日：2022-09-29
申请号：US17654537
申请日：2022-03-11
IPC分类号： G06F9/4401 , G06F9/30
摘要： In an embodiment, a hardware configuration circuit reads and decodes an encoded life-cycle data and provides the decoded life-cycle data to a hardware circuit. A reset circuit monitors an external reset signal received via a reset terminal and, in response to determining that the external reset signal has a first logic level, executes a reset, a configuration, and a wait phase. The reset circuit waits until the external reset signal has a second logic level. A communication interface is activated during the wait phase and configured to receive a request. A hardware verification circuit generates a life-cycle advancement request signal when the request includes a given reference password and a reset circuit is in the wait phase. A write circuit writes a bit of the encoded life-cycle data stored in a non-volatile memory when the life-cycle advancement request signal is set, advancing the life-cycle to a given predetermined life-cycle stage.
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公开(公告)号：US20220271663A1
公开(公告)日：2022-08-25
申请号：US17650463
申请日：2022-02-09
摘要： A power supply system includes a voltage application source, and a switched mode power supply having an output coupled to the voltage application source through a first path and through a second path different from the first path. A first node is coupled to the output of the switched mode power supply, the switched mode power supply being configured to couple the first node to the voltage application source through the first path in a first operating mode and through the second path in a different second operating mode. A digital regulator is coupled to the first node. A digital circuit is coupled to an output of the digital regulator. An analog regulator is coupled to the first node and an analog circuit coupled to an output of the analog regulator.
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公开(公告)号：US20220230682A1
公开(公告)日：2022-07-21
申请号：US17657861
申请日：2022-04-04
摘要： A phase-change memory device column decoder is divided into two portions that can be governed independently of one another, and the driving signals of the two portions are configured so as to guarantee comparable capacitive loads at the two inputs of a sense amplifier in both of the operations of single-ended reading and double-ended reading. In particular, during single-ended reading, the sense amplifier has a first input that receives a capacitive load corresponding to the direct memory cell selected, and a second input that receives a capacitive load associated to a non-selected complementary memory cell.
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公开(公告)号：US20220155519A1
公开(公告)日：2022-05-19
申请号：US17649520
申请日：2022-01-31
发明人： Frédéric Boeuf , Luca Maggi
摘要： A photonic integrated circuit chip includes vertical grating couplers defined in a first layer. Second insulating layers overlie the vertical grating coupler and an interconnection structure with metal levels is embedded in the second insulating layers. A cavity extends in depth through the second insulating layers all the way to an intermediate level between the couplers and the metal level closest to the couplers. The cavity has lateral dimensions such that the cavity is capable of receiving a block for holding an array of optical fibers intended to be optically coupled to the couplers.
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