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1.发明申请公开(公告)号：US20180149504A1
公开(公告)日：2018-05-31
申请号：US15477285
申请日：2017-04-03
IPC分类号： G01F1/66
摘要： A flow meter for determining the flow rate of a fluid through a conduit, including an upper body having an inlet chamber, an acoustic channel, an outlet chamber, a sound wave generator, and a sound wave receiver. The inlet chamber, acoustic channel, and outlet chamber are fluidly connected together. The acoustic channel is a non-linear pathway that is symmetrically dimensioned. The sound wave generator is configured to create a sound wave that moves along the liquid pathway formed by the acoustic channel. The receiver detects that sound wave that has moved through the acoustic channel and such information is used to determine the flow rate of the fluid through the flow meter.
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公开(公告)号：US20180097513A1
公开(公告)日：2018-04-05
申请号：US15282957
申请日：2016-09-30
发明人： Michael Couleur , Neil Gibson , Antonio Priego
CPC分类号： H03K7/06 , H02M3/07 , H02M3/156 , H02M2001/0006 , H02M2001/0035 , H02M2001/0048 , H03K3/033 , H03L5/02 , H03L7/0812 , H03L7/089
摘要： Disclosed examples include self-biased DLL circuits to generate a bias current signal proportional to a repetition frequency of a first signal representing continuous switching or discontinued switching operation of the DC-DC converter. The DLL circuit includes a monostable multivibrator to provide a pulse output signal in response to an edge of the first signal with a pulse duration set by a control current signal, a phase detector to provide output signals according to a phase difference between an edge of the pulse output signal and the first signal, and an output circuit to provide an output signal according to the phase detector output signals and according to an offset signal, to provide the bias current signal according to the output signal, and to provide the control current signal according to the output signal.
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公开(公告)号：US09929650B1
公开(公告)日：2018-03-27
申请号：US15274024
申请日：2016-09-23
发明人： Joerg Kirchner , Hermann Seibold , Ivo Huber
CPC分类号： H02M3/158 , H02M1/00 , H02M1/08 , H02M1/14 , H02M1/44 , H02M3/156 , H02M3/157 , H02M2001/0009
摘要： Methods and apparatus for operating a DC-to-DC voltage converter that has a power stage that includes at least one switching transistor. The output voltage of the DC-to-DC voltage converter is monitored. If the output voltage drops below a lower output voltage threshold, a series of drive pulses is provided to the at least one switching transistor to commence switching of the at least one switching transistor. If the output voltage rises above an upper output voltage threshold, a random number of additional drive pulses is provided to the at least one switching transistor and then the provision of drive pulses to the at least one switching transistor is ceased.
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公开(公告)号：US09887701B1
公开(公告)日：2018-02-06
申请号：US15261898
申请日：2016-09-10
CPC分类号： H03K23/40
摘要： In described examples, an apparatus includes: a counter configured to receive a reference clock signal and having a next state input and a current state output; a multiplexer coupled to the next state input of the counter, configured to output one of an incremented next state value and a corrected next state count value responsive to a count correction select control signal; a seconds reference circuit coupled to the current state output of the counter, configured to output a seconds reference signal; an incrementer coupled to the current state output of the counter, configured to output the incremented next state value; and a calibration compensation circuit coupled to a compensate up down input signal and to the current state output of the counter, configured to output the corrected next state count value and the count correction select control signal.
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公开(公告)号：US09780644B1
公开(公告)日：2017-10-03
申请号：US15220092
申请日：2016-07-26
CPC分类号： G06F1/10 , G06F1/3237 , H03K19/0016
摘要： An apparatus includes: a voltage regulator that outputs a voltage responsive to an enable signal; a power managed domain coupled to the voltage regulator and including a clock generator configured to output a clock signal from the clock generator; and an always on domain. The always on domain receives the clock signal. The always on domain includes a finite state machine coupled to receive the clock signal and receiving a shutdown request signal. The finite state machine is configured to output a signal to control power to the power managed domain and to disable the clock generator, responsive to the shutdown request signal. The finite state machine receives an asynchronous wake signal, and circuitry in the always on domain is coupled to enable power to the power managed domain and to the clock generator, responsive to the asynchronous wake input signal.
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公开(公告)号：US09704944B2
公开(公告)日：2017-07-11
申请号：US13781179
申请日：2013-02-28
CPC分类号： H01L28/20 , H01L27/016 , H01L27/0802 , H01L28/24
摘要： An integrated circuit contains three thin film resistors over a dielectric layer. The first resistor body includes only a bottom thin film layer and the first resistor heads include the bottom thin film layer, a middle thin film layer and a top thin film layer. The second resistor body and heads include all three thin film layers. The third resistor body does not include the middle thin film layer. The three resistors are formed using two etch masks.
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公开(公告)号：US09672781B2
公开(公告)日：2017-06-06
申请号：US14989424
申请日：2016-01-06
IPC分类号： G09G3/36
CPC分类号： G09G3/3655 , G09G3/3659 , G09G3/3674 , G09G3/3685 , G09G2310/0289 , G09G2330/023
摘要： A level shifter circuit has a plurality of channels for providing signals to a capacitive load and has circuits for sharing charge stored in the capacitive load between the channels. A first pair of channel clock generating circuits are coupled respectively to a first pair of channels. A second pair of channel clock generating circuits are coupled respectively to a second pair of channels. A pair of switches couple the first pair of channels together and the second pair of channels together, respectively, for sharing charge between the channels. A single resistor is coupled in circuit with all of the channels for controlling a slope of charge sharing between channels.
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公开(公告)号：US09665116B1
公开(公告)日：2017-05-30
申请号：US14942460
申请日：2015-11-16
发明人： Matthias Arnold , Asif Qaiyum
CPC分类号： G05F3/16
摘要： A proportional to absolute temperature (PTAT) generator generates a current PTAT (IPTAT) and a fractional VBE in a first regulation loop. A level shifting voltage-to-current converter is arranged as a second regulation loop and is operable to generate a current ZTC (IZTC) and/or a voltage ZTC (VZTC). Both regulation loops are nested into each other. In an embodiment, the voltage-to-current converter is operable to sum a scaled voltage PTAT (VPTAT/Y) with the fractional VBE (VBE/X) to generate the ZTC signal. In another embodiment, the voltage-to-current converter is operable to sum a delta voltage threshold (ΔVTH) with the fractional VBE (VBE/X) to generate the ZTC signal.
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公开(公告)号：US09654131B1
公开(公告)日：2017-05-16
申请号：US15054220
申请日：2016-02-26
CPC分类号： H03M1/1071 , H03M1/1038 , H03M1/466 , H03M1/468 , H03M5/00 , H03M7/165
摘要： An analog-to-digital converter (ADC) includes a digital-to-analog converter (DAC) that has a configurable capacitor array. Based on measurements of differential nonlinearity (DNL) and/or integral nonlinearity (INL) error by an external test computer system, an order for use of the DAC's capacitors can be determined so as to reduce DNL error aggregation, also called INL. The DAC includes a switch matrix that can be programmed by programming data supplied by the test computer system.
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公开(公告)号：US09606563B2
公开(公告)日：2017-03-28
申请号：US14247918
申请日：2014-04-08
摘要： An integrated circuit is provided with a bandgap voltage reference circuit having a bandgap reference voltage output. A bandgap failure detection circuit is coupled to the bandgap reference voltage output. The bandgap failure detection forms a model value of the reference voltage from a first time, compares a present value of the reference voltage at a second time to the model value; and asserts a bandgap fail signal to indicate when the present value is less than the model value by a threshold value. The integrated circuit is reset by the bandgap fail signal. The detection circuit may be operated from a failsafe voltage domain that also allows a critical circuit to complete a pending operation during a reset.
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