Analog-to-digital conversion systems and methods with pulse generators

    公开(公告)号:US12063445B2

    公开(公告)日:2024-08-13

    申请号:US17362876

    申请日:2021-06-29

    发明人: Kevin N. Ye

    IPC分类号: H04N25/75 H03M1/52 H03M1/56

    CPC分类号: H04N25/75 H03M1/52 H03M1/56

    摘要: Techniques are disclosed for analog-to-digital conversion systems and methods with pulse generators. In one example, an imaging system includes an analog-to-digital converter (ADC). The ADC includes a comparator configured to generate a comparator output signal based on a first signal and a second signal. The comparator output signal is associated with a first state or a second state. The ADC further includes a pulse generator coupled to the comparator. The pulse generator is configured to generate a pulse signal in response to a transition of the comparator output signal from the first state to the second state. The ADC further includes a memory device coupled to the pulse generator. The memory device is configured to capture a counter value from a counter circuit in response to the pulse signal. The counter value is associated with the detector signal. Related methods are also provided.

    Superlattice-based detector systems and methods

    公开(公告)号:US12057465B2

    公开(公告)日:2024-08-06

    申请号:US17344210

    申请日:2021-06-10

    发明人: Edward K. Huang

    摘要: Techniques are disclosed for facilitating detection of electromagnetic radiation using superlattice-based detector systems and methods. In one example, an infrared detector includes a first superlattice structure including first periods. Each of the first periods includes a first sub-layer and a second sub-layer adjacent to the first sub-layer. The first and second sub-layers include first and second semiconductor materials. The infrared detector further includes a second superlattice structure disposed on the first superlattice structure. The second superlattice structure includes second periods. Each of the second periods includes a third sub-layer and a fourth sub-layer adjacent to the third sub-layer. The third-sub-layer includes a third semiconductor material. The fourth sub-layer includes a fourth semiconductor material. A p-n junction is formed at an interface within the second superlattice structure or at an interface between the first and second superlattice structures.

    Dual color detection systems and methods

    公开(公告)号:US12004358B2

    公开(公告)日:2024-06-04

    申请号:US17222931

    申请日:2021-04-05

    发明人: Edward K. Huang

    摘要: Techniques are disclosed for facilitating dual color detection. In one example, an imaging device includes a first pixel configured to detect first image data associated with a first waveband of electromagnetic radiation. The imaging device further includes a second pixel configured to detect second image data associated with a second waveband of the electromagnetic radiation, where at least a portion of the second waveband does not overlap the first waveband. The imaging device further includes a bias circuit configured to apply a first voltage between the first pixel and a first ground contact, and apply a second voltage between the second pixel and a second ground contact. The first voltage is different from the second voltage. Related methods are also provided.

    Image color correction systems and methods

    公开(公告)号:US11924590B2

    公开(公告)日:2024-03-05

    申请号:US17701629

    申请日:2022-03-22

    IPC分类号: G06K9/00 H04N9/64

    CPC分类号: H04N9/646

    摘要: Techniques for facilitating image color correction are provided. In one example, a method includes receiving an image. The method further includes determining, based at least on the image, a first scaling value and a second scaling value. The method further includes applying the first scaling value to the image to obtain a scaled image. The method further includes applying a color correction matrix (CCM) to the scaled image to obtain a CCM image. The method further includes applying the second scaling value to the CCM image to obtain a color corrected image. Related devices and systems are also provided.

    CRYOCOOLER MAGNETIC DISPLACER SPRING
    8.
    发明公开

    公开(公告)号:US20230288103A1

    公开(公告)日:2023-09-14

    申请号:US18180048

    申请日:2023-03-07

    IPC分类号: F25B9/14

    摘要: A cryocooler is disclosed. The cryocooler may include a magnetic spring, a regenerator/displacer, a working fluid, and a cold finger configured to contain the working fluid in a closed system, and to contain the regenerator/displacer that is configured to travel linearly within the cold finger. The magnetic spring may provide a force to cause the regenerator/displacer to return to a center position during thermal cycle operation of the cryocooler. Additional systems and related methods are also provided.

    IMAGER VERIFICATION SYSTEMS AND METHODS

    公开(公告)号:US20230131678A1

    公开(公告)日:2023-04-27

    申请号:US18068453

    申请日:2022-12-19

    摘要: Techniques for facilitating imager verification systems and methods are provided. In one example, an imaging device includes a focal plane array. The focal plane array includes a detector array including a plurality of detectors, where each of the plurality of detectors is configured to detect electromagnetic radiation to obtain image data. The focal plane array further includes a readout circuit configured to perform a readout to obtain the image data from each of the plurality of detectors. The imaging device further includes a processing circuit configured to perform a verification of the imaging device based at least on the image data. Related methods and systems are also provided.

    Radar data processing systems and methods

    公开(公告)号:US11609301B2

    公开(公告)日:2023-03-21

    申请号:US16808307

    申请日:2020-03-03

    摘要: Techniques to facilitate radar data processing are disclosed. In one example, a radar system includes a frame generation circuit and a frame processing circuit. The frame generation circuit is configured to receive radar signals. The frame generation circuit is further configured to convert the radar signals to at least one frame having a camera interface format. The frame processing circuit is configured to receive the at least one frame via a camera interface. The frame processing circuit is further configured to process the at least one frame. Related methods and devices are also provided.