公开(公告)号：US20230411548A1

公开(公告)日：2023-12-21

申请号：US18035725

申请日：2021-10-22

Applicant: HUMBOLDT-UNIVERSITAT ZU BERLIN ,  FRAUNHOFER-GESELLSCHAFT ZUR FORDERUNG DERANGEWANDTEN FORSCHUNG E.V.

Inventor： William Ted MASSELINK ,  Mykhaylo Petrovych SEMTSIV ,  Bjöm GLOBISCH

IPC: H01L31/09 ,  H01L31/0304 ,  H01L31/18 ,  H01L31/0352

CPC classification number: H01L31/09 ,  H01L31/03046 ,  H01L31/03042 ,  H01L31/1844 ,  H01L31/035263

Abstract: The invention relates inter alia to a photoconductor (10) comprising a multilayer (13) which comprises a plurality of photoconductive semiconductor layers (131-134). According to the invention, the multilayer (13) comprises at least two sublayers (130) which each comprise at least a first photoconductive semiconductor layer (131) and a second photoconductive semiconductor layer (132), wherein the first and the second photoconductive semiconductor layer (131, 132) are doped to different degrees for each of the sublayers (130).

公开(公告)号：US20180182789A1

公开(公告)日：2018-06-28

申请号：US15580817

申请日：2016-09-05

Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION

Inventor： SUSUMU INOUE ,  YUHI YORIKADO ,  ATSUSHI TODA

IPC: H01L27/146 ,  H01L31/107 ,  H04N5/374

CPC classification number: H01L27/1462 ,  H01L21/02107 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02183 ,  H01L21/02189 ,  H01L21/02192 ,  H01L27/14607 ,  H01L27/1461 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/1463 ,  H01L27/14636 ,  H01L27/14638 ,  H01L27/1464 ,  H01L27/14647 ,  H01L27/14685 ,  H01L27/14689 ,  H01L31/02005 ,  H01L31/02027 ,  H01L31/02162 ,  H01L31/022408 ,  H01L31/028 ,  H01L31/0304 ,  H01L31/0352 ,  H01L31/035263 ,  H01L31/03529 ,  H01L31/1013 ,  H01L31/107 ,  H01L31/1804 ,  H01L31/1808 ,  H01L31/184 ,  H04N9/0451

Abstract: The present technology relates to a solid-state image sensing device for preventing a reduction in light receiving sensitivity of an avalanche photodiode, an electronic device, and a method for manufacturing the solid-state image sensing device. A solid-state image sensing device includes an avalanche photodiode having a first region of a first conductive type, a second region of a second conductive type different from the first conductive type, and an avalanche region sandwiched between the first region and the second region, which extend in a thickness direction of a semiconductor substrate, and a film formed on at least one side of the semiconductor substrate and including a metal oxide film, a metal nitride film, or a mix crystal-based film of metal oxide film and metal nitride film. The present technology can be applied to CMOS image sensors, for example.

公开(公告)号：US09548408B2

公开(公告)日：2017-01-17

申请号：US14686489

申请日：2015-04-14

Applicant: L-3 Communications Cincinnati Electronics Corporation

Inventor： Yajun Wei

IPC: H01L31/0352 ,  H01L31/101 ,  H01L31/109 ,  H01L31/0304

CPC classification number: H01L31/035263 ,  H01L31/022408 ,  H01L31/03046 ,  H01L31/032 ,  H01L31/035209 ,  H01L31/035236 ,  H01L31/035272 ,  H01L31/072 ,  H01L31/101 ,  H01L31/1013 ,  H01L31/109 ,  H01L31/1844 ,  Y02E10/544

Abstract: Embodiments of the present disclosure are directed to infrared detector devices incorporating a tunneling structure. In one embodiment, an infrared detector device includes a first contact layer, an absorber layer adjacent to the first contact layer, and a tunneling structure including a barrier layer adjacent to the absorber layer and a second contact layer adjacent to the barrier layer. The barrier layer has a tailored valence band offset such that a valence band offset of the barrier layer at the interface between the absorber layer and the barrier layer is substantially aligned with the valence band offset of the absorber layer, and the valence band offset of the barrier layer at the interface between the barrier layer and the second contact layer is above a conduction band offset of the second contact layer.

Abstract translation: 本公开的实施例涉及结合隧道结构的红外检测器装置。 在一个实施例中，红外检测器装置包括第一接触层，与第一接触层相邻的吸收层，以及包括邻近吸收层的阻挡层和与阻挡层相邻的第二接触层的隧道结构。 阻挡层具有定制的价带偏移，使得阻挡层在吸收层和阻挡层之间的界面处的价带偏移基本上与吸收层的价带偏移对准，并且 在阻挡层和第二接触层之间的界面处的阻挡层高于第二接触层的导带偏移。

公开(公告)号：US09543456B1

公开(公告)日：2017-01-10

申请号：US14547055

申请日：2014-11-18

Applicant: Magnolia Solar, Inc.

Inventor： Roger E. Welser ,  Ashok K. Sood

IPC: H01L31/00 ,  H01L31/0216 ,  H01L31/0725 ,  H01L31/0735 ,  H01L31/18

CPC classification number: H01L31/1884 ,  G02B1/115 ,  H01L31/0203 ,  H01L31/02165 ,  H01L31/02168 ,  H01L31/022425 ,  H01L31/022475 ,  H01L31/03046 ,  H01L31/035236 ,  H01L31/035263 ,  H01L31/0445 ,  H01L31/048 ,  H01L31/056 ,  H01L31/065 ,  H01L31/0725 ,  H01L31/0735 ,  H01L31/184 ,  H01L31/1844 ,  Y02E10/52 ,  Y02E10/544

Abstract: Material and antireflection structure designs and methods of manufacturing are provided that produce efficient photovoltaic power conversion from single- and multi-junction devices. Materials of different energy gap are combined in the depletion region of at least one of the semiconductor junctions. Higher energy gap layers are positioned to reduce the diode dark current and enhance the operating voltage by suppressing both carrier injections across the junction and recombination rates within the junction. Step-graded antireflection structures are placed above the active region of the device in order to increase the photocurrent.

Abstract translation: 提供材料和抗反射结构设计和制造方法，其从单和多结装置产生高效的光伏电力转换。 不同能隙的材料组合在至少一个半导体结的耗尽区中。 定位更高的能隙层以减少二极管暗电流并且通过抑制跨结的载流子注入和结中的复合速率来提高工作电压。 步进渐变防反射结构放置在器件的有源区上方，以增加光电流。

公开(公告)号：US09070803B2

公开(公告)日：2015-06-30

申请号：US13105422

申请日：2011-05-11

Applicant: Shuqiang Yang ,  Michael N. Miller ,  Mohamed M. Hilali ,  Fen Wan ,  Gerard M. Schmid ,  Liang Wang ,  Sidlgata V. Sreenivasan ,  Frank Y. Xu

Inventor： Shuqiang Yang ,  Michael N. Miller ,  Mohamed M. Hilali ,  Fen Wan ,  Gerard M. Schmid ,  Liang Wang ,  Sidlgata V. Sreenivasan ,  Frank Y. Xu

IPC: H01L31/00 ,  H01L31/0352 ,  B82Y20/00 ,  H01L31/0224 ,  H01L31/0236 ,  H01L31/0376 ,  H01L31/0392 ,  H01L31/075 ,  H01L31/076 ,  H01L31/20 ,  H01L31/0463

CPC classification number: H01L31/02363 ,  B82Y20/00 ,  C23C14/34 ,  H01L31/022466 ,  H01L31/0236 ,  H01L31/035263 ,  H01L31/035281 ,  H01L31/03762 ,  H01L31/0392 ,  H01L31/03921 ,  H01L31/03926 ,  H01L31/0463 ,  H01L31/075 ,  H01L31/076 ,  H01L31/202 ,  Y02E10/548 ,  Y02P70/521

Abstract: Systems and methods for fabrication of nanostructured solar cells having arrays of nanostructures are described, including nanostructured solar cells having a repeating pattern of pyramid nanostructures, providing for low cost thin-film solar cells with improved PCE.

公开(公告)号：US08829336B2

公开(公告)日：2014-09-09

申请号：US11744010

申请日：2007-05-03

Applicant: Ryne P. Raffaelle ,  David M. Wilt

Inventor： Ryne P. Raffaelle ,  David M. Wilt

IPC: H01L31/05 ,  H01L31/075 ,  B82Y20/00 ,  H01L27/142 ,  H01L31/0352

CPC classification number: H01L27/1423 ,  B82Y20/00 ,  H01L31/0352 ,  H01L31/035236 ,  H01L31/035263 ,  Y02E10/50

Abstract: A photovoltaic device includes one or more structures, an array of at least one of quantum dots and quantum dashes, at least one groove, and at least one conductor. Each of the structures comprises an intrinsic layer on one of an n type layer and a p type layer and the other one of the n type layer and the p type layer on the intrinsic layer. The array of at least one of quantum dots and quantum dashes is located in the intrinsic layer in at least one of the structures. The groove extends into at least one of the structures and the conductor is located along at least a portion of the groove.

Abstract translation: 光伏器件包括一个或多个结构，量子点和量子破折号中的至少一个的阵列，至少一个沟槽和至少一个导体。 每个结构包括在n型层和p型层之一上的本征层，在本征层上包括n型层和p型层中的另一层。 量子点和量子破折号中的至少一个的阵列位于至少一个结构中的本征层中。 凹槽延伸到至少一个结构中，并且导体沿着凹槽的至少一部分定位。

公开(公告)号：US08461541B2

公开(公告)日：2013-06-11

申请号：US12794627

申请日：2010-06-04

Applicant: Francisco Garcia ,  Risto Orava ,  Manuel Lozano ,  Giulio Pellegrini

Inventor： Francisco Garcia ,  Risto Orava ,  Manuel Lozano ,  Giulio Pellegrini

IPC: G01T1/24 ,  H01L31/115

CPC classification number: H01L27/14603 ,  H01L27/1446 ,  H01L27/14634 ,  H01L27/14683 ,  H01L31/035263 ,  H01L31/035281

Abstract: A radiation detector is disclosed. The detector has an entrance opening etched through a low-resistivity volume of silicon, a sensitive volume of high-resistivity silicon for converting the radiation particles into detectable charges, and a passivation layer between the low and high-resistivity silicon layers. The detector also has electrodes built in the form of vertical channels for collecting the charges generated in the sensitive volume, and read-out electronics for generating signals based on the collected charges.

Abstract translation: 公开了一种辐射检测器。 检测器具有通过低电阻率体积的硅蚀刻的入口开口，用于将辐射粒子转换成可检测电荷的敏感体积的高电阻率硅，以及低电阻率硅层和高电阻率硅层之间的钝化层。 检测器还具有内置垂直通道形式的电极，用于收集敏感体积中产生的电荷，以及读出电子装置，用于根据收集的电荷产生信号。

公开(公告)号：US20080011349A1

公开(公告)日：2008-01-17

申请号：US11744010

申请日：2007-05-03

Applicant: Ryne Raffaele ,  David Wilt

Inventor： Ryne Raffaele ,  David Wilt

IPC: H01L31/042 ,  H01L21/00 ,  H01L31/00

CPC classification number: H01L27/1423 ,  B82Y20/00 ,  H01L31/0352 ,  H01L31/035236 ,  H01L31/035263 ,  Y02E10/50

Abstract: A photovoltaic device includes one or more structures, an array of at least one of quantum dots and quantum dashes, at least one groove, and at least one conductor. Each of the structures comprises an intrinsic layer on one of an n type layer and a p type layer and the other one of the n type layer and the p type layer on the intrinsic layer. The array of at least one of quantum dots and quantum dashes is located in the intrinsic layer in at least one of the structures. The groove extends into at least one of the structures and the conductor is located along at least a portion of the groove.

Abstract translation: 光伏器件包括一个或多个结构，量子点和量子破折号中的至少一个的阵列，至少一个沟槽和至少一个导体。 每个结构包括在n型层和p型层之一上的本征层，在本征层上包括n型层和p型层中的另一层。 量子点和量子破折号中的至少一个的阵列位于至少一个结构中的本征层中。 凹槽延伸到至少一个结构中，并且导体沿着凹槽的至少一部分定位。

公开(公告)号：US20240297261A1

公开(公告)日：2024-09-05

申请号：US18593512

申请日：2024-03-01

Applicant: LandMark Optoelectronics Corporation

Inventor： Hung-Wen HUANG ,  Yung-Chao CHEN ,  Yi-Hsiang WANG ,  Wei LIN

IPC: H01L31/0216 ,  H01L31/0352

CPC classification number: H01L31/02164 ,  H01L31/035263

Abstract: A semiconductor device includes a substrate, a buffer layer, a gradient layer, an active layer, a window layer, and an optical filtering layer. The substrate includes a first element and a second element. The buffer layer is disposed on the substrate. The gradient layer is formed on the buffer layer, and includes sublayers. Each sublayer includes the first, second, and third elements. For each sublayer, a lattice constant thereof is adjusted by changing a ratio of the second element to the third element. The active layer is formed on the gradient layer, and includes the first, second, and third elements. The window layer is formed on the active layer. The optical filtering layer includes the first, second, and third elements, and is formed on the window layer to block a portion of light having a wavelength in a predetermined wavelength range.

公开(公告)号：US09911889B2

公开(公告)日：2018-03-06

申请号：US15699436

申请日：2017-09-08

Applicant: QATAR UNIVERSITY ,  TEXAS A&M UNIVERSITY SYSTEM

Inventor： Aditya Chandra Sai Ratcha ,  Amit Verma ,  Reza Nekovei ,  Mahmoud M. Khader

IPC: H01L21/74 ,  H01L31/11 ,  H01L31/18 ,  H01L31/0352 ,  H01L31/0304

CPC classification number: H01L31/1105 ,  H01L31/03046 ,  H01L31/035263 ,  H01L31/03529 ,  H01L31/1844

Abstract: Certain embodiments of the present invention may be directed to a transistor structure. The transistor structure may include a semiconductor substrate. The semiconductor substrate may include a drift region, a collector region, an emitter region, and a lightly-doped/undoped region. The lightly-doped/undoped region may be lightly-doped and/or undoped. The transistor structure may also include a heterostructure. The heterostructure forms a heterojunction with the lightly-doped/undoped region. The transistor structure may also include a collector terminal. The collector terminal is in contact with the collector region. The transistor structure may also include a gate terminal. The gate terminal is in contact with the heterostructure. The transistor structure may also include an emitter terminal. The emitter terminal is in contact with the lightly-doped/undoped region and the emitter region.