公开(公告)号：US07276946B2

公开(公告)日：2007-10-02

申请号：US10892805

申请日：2004-07-16

申请人： Feng Lin

发明人： Feng Lin

IPC分类号： H03L7/00

CPC分类号： H03L7/0812

摘要： Measure-controlled delay (MCD) circuits include a measure circuit and sample circuit for synchronizing an output clock to an input clock. In response to triggering of the measure circuit, sample circuits sample outputs of a measure delay array. Sample reset logic prevents output of the output clock when any of a predetermined one or more of the samples correspond to a particular logic value (i.e., logic “1” or “0”). For example, sample reset logic may prevent an MCD circuit from providing the output clock when a sample taken from the earliest sampling point of the measure delay array corresponds to logic “1.” The MCD circuit may then provide the output clock in response to a subsequent triggering for which a sample taken from the earliest sampling point is logic “0.” Phase error of the output clock is thereby reduced. MCD circuits improve response to process, voltage and temperature (PVT) variations.

摘要翻译： 测量控制延迟（MCD）电路包括用于将输出时钟同步到输入时钟的测量电路和采样电路。 响应于测量电路的触发，采样电路对测量延迟阵列的输出进行采样。 当预定的一个或多个采样中的任一个对应于特定逻辑值（即，逻辑“1”或“0”）时，采样复位逻辑防止输出时钟的输出。 例如，当从测量延迟阵列的最早采样点采样的样本对应于逻辑“1”时，采样复位逻辑可以防止MCD电路提供输出时钟。 然后，MCD电路可以响应于从最早采样点采集的样本为逻辑“0”的后续触发来提供输出时钟。 从而降低了输出时钟的相位误差。 MCD电路改善了对工艺，电压和温度（PVT）变化的响应。

公开(公告)号：US07268582B1

公开(公告)日：2007-09-11

申请号：US11286038

申请日：2005-11-22

申请人： Michael M Zheng ,  Binh Ton ,  Chong H Lee

发明人： Michael M Zheng ,  Binh Ton ,  Chong H Lee

IPC分类号： H03K19/173

CPC分类号： H03K19/17744 ,  H03K19/17732

摘要： An I/O interface for configuring hard IP embedded in a FPGA includes a register load signal, a CSR initialization signal, and a register data signal. After programming the DPRIO registers, the register data controls the operation of the hard IP block. The interface supports both CSR load mode and the MDIO interface. The user-friendly I/O interface eliminates all requirements on the end-user and is virtually transparent to the end-user.

摘要翻译： 用于配置嵌入在FPGA中的硬IP的I / O接口包括寄存器加载信号，CSR初始化信号和寄存器数据信号。 在编程DPRIO寄存器之后，寄存器数据控制硬IP块的操作。 该接口支持CSR负载模式和MDIO接口。 用户友好的I / O接口消除了对最终用户的所有要求，对最终用户实际上是透明的。

公开(公告)号：US07266833B2

公开(公告)日：2007-09-04

申请号：US10453388

申请日：2003-06-03

申请人： Thomas Edward Ward, III ,  Ted Nesson

发明人： Thomas Edward Ward, III ,  Ted Nesson

IPC分类号： G06F3/00

CPC分类号： H04N21/44222 ,  G06Q30/02 ,  H04N5/44543 ,  H04N5/45 ,  H04N7/165 ,  H04N21/23614 ,  H04N21/252 ,  H04N21/26283 ,  H04N21/42204 ,  H04N21/4316 ,  H04N21/44016 ,  H04N21/4524 ,  H04N21/47 ,  H04N21/47214 ,  H04N21/4722 ,  H04N21/478 ,  H04N21/4782 ,  H04N21/482 ,  H04N21/4825 ,  H04N21/812

摘要： A system and method for utilizing data stored in an EPG database for modifying advertisement information. In this way, a service provider and/or an advertiser can transmit a single advertisement to all the television stations regardless of their geographic location and other user specific information, and need not re-transmit the advertisement even if there is a change in the show's program description. When the advertisement is displayed, the correct updated information is retrieved from the EPG database and inserted into the advertisement.In one aspect, the present invention describes a method for modifying an advertisement in an EPG comprising the steps of: storing television schedule information in a first database; storing advertisement information in a second database; incorporating a portion of the television schedule information into a portion of the advertisement information to form a modified advertisement; and displaying the modified advertisement on a screen.

摘要翻译： 一种用于利用存储在EPG数据库中的数据来修改广告信息的系统和方法。 以这种方式，服务提供商和/或广告商可以向所有电视台发送单个广告，而不管其地理位置和其他用户特定信息如何，并且不需要重新发送广告，即使节目的变化 节目描述。 当显示广告时，从EPG数据库检索正确的更新信息并将其插入到广告中。 一方面，本发明描述了一种用于修改EPG中的广告的方法，包括以下步骤：将电视节目表信息存储在第一数据库中; 将广告信息存储在第二数据库中; 将所述电视节目表信息的一部分合并到所述广告信息的一部分中以形成修改的广告; 并在屏幕上显示修改的广告。

公开(公告)号：US07260962B2

公开(公告)日：2007-08-28

申请号：US10796332

申请日：2004-03-08

申请人： Michael Lax ,  Agjah I Libohova

发明人： Michael Lax ,  Agjah I Libohova

IPC分类号： B65D85/67

CPC分类号： B65D50/067 ,  E05B73/0023 ,  G11B33/0427 ,  Y10T70/5004 ,  Y10T70/5031 ,  Y10T70/7057

摘要： A lockable storage case includes a top cover pivotably coupled to a bottom cover through a spine. The top cover includes loops or an upper lock receiving member and a lower lock receiving member defining a top cover lock insertion path. The bottom cover includes loops or an upper lock receiving member and a lower lock receiving member defining a bottom cover lock insertion path. The lower lock receiving members of both the top and bottom covers include hooks for receiving and maintaining a latch. When the top cover is closed on the bottom cover, the top and bottom cover insertion paths combine to form a combined lock insertion path. A lock for the storage case includes first and second catch mechanisms with first and second catches. To lock the storage case, the lock is inserted into the combined lock insertion path so that the catches on the lock mate with and are retained with the hooks in the top and bottom covers.

摘要翻译： 可锁定的存储箱包括通过脊柱可枢转地联接到底盖的顶盖。 顶盖包括环或上锁定接收构件和限定顶盖锁插入路径的下锁定接收构件。 底盖包括环或上锁定接收构件和限定底盖锁插入路径的下锁定接收构件。 顶部和底部盖的下部锁定接收构件都包括用于接收和保持闩锁的钩子。 当顶盖在底盖上关闭时，顶盖和底盖插入路径组合形成组合的锁插入路径。 用于存储箱的锁包括具有第一和第二捕获的第一和第二捕获机构。 为了锁定储物盒，锁被插入到组合的锁插入路径中，使得锁上的卡扣与顶盖和底盖中的钩子配合并保持。

公开(公告)号：US07257803B1

公开(公告)日：2007-08-14

申请号：US11224156

申请日：2005-09-12

申请人： Steven J E Wilton ,  Kimberly Bozman ,  Noha Kafafi ,  James Wu

发明人： Steven J E Wilton ,  Kimberly Bozman ,  Noha Kafafi ,  James Wu

IPC分类号： G06F17/50

CPC分类号： G06F17/5054

摘要： Integrated circuit devices having fixed and programmable logic portions are made by combining a hardware description language representation of the fixed logic and a hardware description language representation of the programmable logic to create a single hardware description language representation of a device. This allows multiple portions of programmable logic, distributed where needed in whatever size needed, to be interspersed among the fixed logic. Because the behavior of the programmable logic, rather than of the user programming, is being represented, a programmable logic architecture is provided that lacks behaviors, such as combinational loops, that would cause compilation of the hardware description language to generate errors.

摘要翻译： 具有固定和可编程逻辑部分的集成电路装置通过组合固定逻辑的硬件描述语言表示和可编程逻辑的硬件描述语言表示来创建设备的单个硬件描述语言表示。 这允许可编程逻辑的多个部分，分布在需要的任何大小的所需尺寸上，以分散在固定逻辑中。 由于可编程逻辑（而不是用户编程）的行为被表示，所以提供了一种可编程逻辑体系结构，其缺少行为，例如组合循环，这将导致硬件描述语言的编译以产生错误。

公开(公告)号：US07256063B2

公开(公告)日：2007-08-14

申请号：US10886648

申请日：2004-07-07

申请人： Joseph F. Pinkerton ,  John C. Harlan ,  Jeffrey D. Mullen

发明人： Joseph F. Pinkerton ,  John C. Harlan ,  Jeffrey D. Mullen

IPC分类号： H01L21/00

CPC分类号： G11C23/00 ,  B81B3/0021 ,  B81B2201/014 ,  B82Y10/00 ,  B82Y30/00 ,  G11C13/025 ,  G11C2213/16 ,  H01H1/0094 ,  H01H1/027 ,  Y10S977/732

摘要： Nanoelectromechanical switch systems (NEMSS) that are structured around the mechanical manipulation of nanotubes are provided. Such NEMSS can realize the functionality of, for example, automatic switches, adjustable diodes, amplifiers, inverters, variable resistors, pulse position modulators (PPMs), and transistors.In one embodiment, a nanotube is anchored at one end to a base member. The nanotube is also coupled to a voltage source. This voltage source creates an electric charge at the tip of the free-moving-end of the nanotube that is representative of the polarity and intensity of the voltage source. The free-moving end of this nanotube can be electrically controlled by applying an electric charge to a nearby charge member layer that is either of the same (repelling) or opposite (attracting) polarity of the nanotube. A contact layer is then placed in the proximity of the free-moving end of the nanotube such that when a particular electric charge is placed on the nanotube, the nanotube electrically couples the contact layer.

摘要翻译： 提供了围绕纳米管的机械操作构建的纳米机电开关系统（NEMSS）。 这样的NEMSS可以实现例如自动开关，可调二极管，放大器，反相器，可变电阻器，脉冲位置调制器（PPM）和晶体管的功能。 在一个实施方案中，纳米管在一端锚定到基底构件。 纳米管还耦合到电压源。 该电压源在纳米管的自由移动端的尖端处产生代表电压源的极性和强度的电荷。 该纳米管的自由移动端可以通过将电荷施加到与纳米管相同（排斥）或相反（吸引））极性的附近的电荷元件层来进行电控制。 然后将接触层放置在纳米管的自由移动端附近，使得当在纳米管上放置特定的电荷时，纳米管电耦合接触层。

公开(公告)号：US07240133B1

公开(公告)日：2007-07-03

申请号：US10964061

申请日：2004-10-12

申请人： Ning Xue

发明人： Ning Xue

IPC分类号： G06F3/00 ,  H03M7/00 ,  H03M7/04 ,  G06F13/12 ,  G06F13/38 ,  G06F13/16

CPC分类号： H04L25/4908 ,  H03M5/145

摘要： A data converter for a padded protocol interface performs, on a first data sample, decoding operations requiring data from second and third data samples, while buffering the second data sample without buffering the third data sample. A state machine controlling the decoding operation waits an additional clock cycle, until the second sample has become the current sample and the third sample has become the second sample and thus is available.

摘要翻译： 用于填充协议接口的数据转换器在第一数据样本上执行需要来自第二和第三数据样本的数据的解码操作，同时缓冲第二数据样本而不缓冲第三数据样本。 控制解码操作的状态机等待另外的时钟周期，直到第二个样本已经成为当前样本，并且第三个样本已经成为第二个样本，因此可用。

公开(公告)号：US07234125B1

公开(公告)日：2007-06-19

申请号：US10874996

申请日：2004-06-23

申请人： Alasdair Scott ,  Gregor Nixon

发明人： Alasdair Scott ,  Gregor Nixon

IPC分类号： G06F17/50

CPC分类号： G06F17/5031

摘要： Programming software for mask-programmable logic devices provides a timing estimation to the user for the user's logic design during the compilation stage, notwithstanding that the software is not aware of the ultimate placement and routing of the design, which will be performed by the mask-programmable logic device supplier. The software includes a timing model based on actual delay measurements for different user designs in similar devices.

摘要翻译： 掩模可编程逻辑器件的编程软件在编译阶段为用户提供了用户逻辑设计的定时估计，尽管软件不知道设计的最终布局和路由，将由掩模可编程逻辑器件执行， 可编程逻辑器件供应商。 该软件包括基于类似设备中不同用户设计的实际延迟测量的时序模型。

公开(公告)号：US07233189B1

公开(公告)日：2007-06-19

申请号：US10996592

申请日：2004-11-24

申请人： Boon Jin Ang ,  Thow Pang Chong

发明人： Boon Jin Ang ,  Thow Pang Chong

IPC分类号： H03K3/00 ,  G06F17/50

CPC分类号： G06F1/10

摘要： Signal transmission circuitry on an integrated circuit ameliorates the effects of possible inequality in rise and fall times of buffer circuits along the transmission circuitry by providing at least one of the buffer circuits as an inverting buffer circuit and at least one other of the buffer circuits as a non-inverting buffer circuit. The invention may be of particular interest for use in clock signal distribution networks on integrated circuits such as programmable logic devices.

摘要翻译： 集成电路上的信号传输电路通过将缓冲电路中的至少一个作为反相缓冲电路和至少另一个缓冲电路来改善沿着传输电路的缓冲电路的上升和下降时间可能的不等式的影响，作为 非反相缓冲电路。 本发明可以特别关注于集成电路（例如可编程逻辑器件）上的时钟信号分配网络。

公开(公告)号：US07230451B1

公开(公告)日：2007-06-12

申请号：US11208906

申请日：2005-08-22

申请人： Martin Langhammer

发明人： Martin Langhammer

IPC分类号： H03K19/177

CPC分类号： H03K19/17736 ,  H03K19/17732

摘要： A programmable logic device (PLD) is provided that includes at least one dedicated output routing channel configured to facilitate the processing of output signals generated by multiple function-specific blocks (FSBs). The output routing channel includes a plurality of functional units that may be programmably selectively chained, wherein each functional unit contains an operational block and output selection logic that are configured to programmably selectively implement any of a variety of operations (e.g., bitwise, logical, arithmetic, etc.) that may be performed on the outputs of single FSBs and/or several FSBs. In addition to the output routing channel, the PLD includes at least one input routing channel that is configured to facilitate the routing, registering, and/or selection of FSB input signals. The FSB input routing channel also includes circuitry for performing elementary processing operations.

摘要翻译： 提供了一种可编程逻辑器件（PLD），其包括至少一个专用输出路由通道，其被配置为便于处理由多个功能特定块（FSB）产生的输出信号。 输出路由信道包括可编程选择性链接的多个功能单元，其中每个功能单元包含操作块和输出选择逻辑，其被配置为可编程选择性地执行各种操作（例如，按位，逻辑，运算 等），其可以在单个FSB和/或几个FSB的输出上执行。 除了输出路由信道之外，PLD还包括至少一个输入路由信道，其被配置为便于FSB输入信号的路由，注册和/或选择。 FSB输入路由信道还包括用于执行基本处理操作的电路。