摘要:
An I/O interface for configuring hard IP embedded in a FPGA includes a register load signal, a CSR initialization signal, and a register data signal. After programming the DPRIO registers, the register data controls the operation of the hard IP block. The interface supports both CSR load mode and the MDIO interface. The user-friendly I/O interface eliminates all requirements on the end-user and is virtually transparent to the end-user.
摘要:
High-speed serial data transceiver circuitry on a programmable logic device (“PLD”) includes some channels that are able to operate at data rates up to a first, relatively low maximum data rate, and other channels that are able to operate at data rates up to a second, relatively high maximum data rate. The relatively low-speed channels are served by relatively low-speed phase locked loop (“PLL”) circuitry, and have other circuit components that are typically needed for handling data that is transmitted at relatively low data rates. The relatively high-speed channels are served by relatively high-speed PLLs, and have other circuit components that are typically needed for handling data that is transmitted at relatively high data rates.
摘要:
A programmable bit error rate monitor includes an error counter, a monitoring period counter with a programmable upper bound to set the monitoring period, and an error flag generator that compares the actual error count to a programmable threshold. The error flag generator may generate flags at different sensitivity levels, and the user may programmably select one of those flags. The three flags can be generated by independent comparators, or they can be extrapolated from the base error flag—e.g., by comparing only certain bits of the error count to corresponding bits of the threshold.
摘要:
A data converter, or “gearbox,” for a padded protocol interface uses a reduced number of components by processing a narrower intermediate data stream, while at the same time multiplying the clock speed of its intermediate input and output so that it processes more data per clock cycle. The data streams can be narrowed to any integer factor of the original width (other than the original width).
摘要:
Phase locked loop circuitry operates digitally, to at least a large extent, to select from a plurality of phase-distributed candidate clock signals the signal that is closest in phase to transitions in another signal such as a clock data recovery (“CDR”) signal. The circuitry is constructed and operated to avoid glitches in the output clock signal that might otherwise result from changes in selection of the candidate clock signal. Frequency division of the candidate clock signals may be used to help the circuitry support serial communication at bit rates below frequencies that an analog portion of the phase locked loop circuitry can economically provide. Over-transmission or over-sampling may be used on the transmit side for similar reasons.
摘要:
An integrated circuit like a programmable logic device (“PLD”) includes a communication channel employing 8B/10B coding. Disparity information determined by 8B/10B decoder circuitry in the communication channel is supplied to other circuitry of the PLD so that any requirement for disparity to have a particular value in conjunction with certain received codes can be checked. On the transmitter side, circuitry is provided for selectively forcing the 8B/10B encoder to use a commanded disparity (which can be either positive or negative) under particular circumstances.
摘要:
Status signals that are generated by one or more FIFO buffers in a high-speed serial interface (“HSSI”) may be combined with transmitted data samples in order to correlate the status signals to the respective data samples. The combined data and status signals may be transmitted either to the subsequent stages of the HSSI datapath or directly to the PLD via a dedicated path with less latency. The combined data and status signals can be used to determine whether a data sample corresponds to a valid data sample or an idle sequence, thereby allowing a user to control the flow of data.
摘要:
Eight-bit ten-bit (8B10B) coding is provided in a hard intellectual property (IP) block with the capability of supporting a greater range of data rates (e.g., data rates less than, equal to, and greater than 3.125 Gbps). Each channel of high speed serial interface circuitry includes receiver circuitry having two 8B10B decoders and transmitter circuitry having two 8B10B encoders. The receiver and transmitter circuitry can be configured to operate in one of three modes of operation: cascade mode, dual channel mode, and single channel mode.
摘要:
A data converter, or “gearbox,” for a padded protocol interface can perform a number of different conversions—e.g., between 64 and 66 bits, between 24 and 26 bits, or between 48 and 50 bits. This is accomplished by clocking the gearbox at different clock speeds, all derived from the same master clock (which may be recovered from the data in a receiver embodiment) using programmable dividers that allow the user to select the clock speed. When the conversion is not that one with the maximum width for which the gearbox is designed, unused bits are ignored. The converter can also find padding bits, for alignment purposes, in data of different widths, again ignoring unused bits when the data are not the widest for which the converter is designed.
摘要:
A programmable logic device (“PLD”) includes communication interface circuitry that can support any of a wide range of communication protocols, including Packet Over Sonet (“POS-5”) and 8-bit/10-bit (“8B10B”) protocols. The interface circuitry includes various functional blocks that are at least partly hard-wired to perform particular types of functions, but that in at least many cases are also partly programmable to allow the basic functions to be adapted for various protocols. Routing of signals to, from, between, and/or around the various functional blocks is also preferably at least partly programmable to facilitate combining the functional blocks in various ways to support various protocols.