DPRIO for embedded hard IP
    1.
    发明授权
    DPRIO for embedded hard IP 有权
    DPRIO用于嵌入式硬IP

    公开(公告)号:US07268582B1

    公开(公告)日:2007-09-11

    申请号:US11286038

    申请日:2005-11-22

    IPC分类号: H03K19/173

    CPC分类号: H03K19/17744 H03K19/17732

    摘要: An I/O interface for configuring hard IP embedded in a FPGA includes a register load signal, a CSR initialization signal, and a register data signal. After programming the DPRIO registers, the register data controls the operation of the hard IP block. The interface supports both CSR load mode and the MDIO interface. The user-friendly I/O interface eliminates all requirements on the end-user and is virtually transparent to the end-user.

    摘要翻译: 用于配置嵌入在FPGA中的硬IP的I / O接口包括寄存器加载信号,CSR初始化信号和寄存器数据信号。 在编程DPRIO寄存器之后,寄存器数据控制硬IP块的操作。 该接口支持CSR负载模式和MDIO接口。 用户友好的I / O接口消除了对最终用户的所有要求,对最终用户实际上是透明的。

    Heterogeneous transceiver architecture for wide range programmability of programmable logic devices
    2.
    发明授权
    Heterogeneous transceiver architecture for wide range programmability of programmable logic devices 有权
    异构收发器架构,用于可编程逻辑器件的广泛可编程性

    公开(公告)号:US07616657B2

    公开(公告)日:2009-11-10

    申请号:US11402417

    申请日:2006-04-11

    IPC分类号: H04J3/00

    摘要: High-speed serial data transceiver circuitry on a programmable logic device (“PLD”) includes some channels that are able to operate at data rates up to a first, relatively low maximum data rate, and other channels that are able to operate at data rates up to a second, relatively high maximum data rate. The relatively low-speed channels are served by relatively low-speed phase locked loop (“PLL”) circuitry, and have other circuit components that are typically needed for handling data that is transmitted at relatively low data rates. The relatively high-speed channels are served by relatively high-speed PLLs, and have other circuit components that are typically needed for handling data that is transmitted at relatively high data rates.

    摘要翻译: 可编程逻辑器件(“PLD”)上的高速串行数据收发器电路包括一些能够以高达第一,相对较低的最大数据速率的数据速率工作的通道,以及能够以数据速率操作的其他通道 达到第二个相对较高的最大数据速率。 相对低速的通道由相对低速的锁相环(“PLL”)电路服务,并且具有通常用于处理以相对低的数据速率发送的数据所需的其他电路组件。 相对高速的信道由相对高速的PLL服务,并且具有通常用于处理以相对高的数据速率传输的数据所需的其他电路部件。

    Programmable bit error rate monitor for serial interface
    3.
    发明授权
    Programmable bit error rate monitor for serial interface 有权
    串行接口的可编程误码率监视器

    公开(公告)号:US07386767B1

    公开(公告)日:2008-06-10

    申请号:US10958447

    申请日:2004-10-05

    申请人: Ning Xue Chong H Lee

    发明人: Ning Xue Chong H Lee

    IPC分类号: G06F11/00

    CPC分类号: G06F11/0772 G06F11/076

    摘要: A programmable bit error rate monitor includes an error counter, a monitoring period counter with a programmable upper bound to set the monitoring period, and an error flag generator that compares the actual error count to a programmable threshold. The error flag generator may generate flags at different sensitivity levels, and the user may programmably select one of those flags. The three flags can be generated by independent comparators, or they can be extrapolated from the base error flag—e.g., by comparing only certain bits of the error count to corresponding bits of the threshold.

    摘要翻译: 可编程误码率监视器包括错误计数器,具有可编程上限的监视周期计数器以设置监视周期,以及将实际错误计数与可编程阈值进行比较的错误标志发生器。 错误标志生成器可以生成不同灵敏度级别的标志,并且用户可以可编程地选择这些标志之一。 这三个标志可以由独立的比较器产生,或者它们可以从基本错误标志中外推,例如通过仅将错误计数的某些位与阈值的相应位进行比较。

    Data converter with reduced component count for padded-protocol interface
    4.
    发明授权
    Data converter with reduced component count for padded-protocol interface 有权
    数据转换器,减少了填充协议接口的组件数量

    公开(公告)号:US07199732B1

    公开(公告)日:2007-04-03

    申请号:US11139083

    申请日:2005-05-26

    申请人: Ning Xue Chong H Lee

    发明人: Ning Xue Chong H Lee

    IPC分类号: H03M7/00

    CPC分类号: H04L25/4908

    摘要: A data converter, or “gearbox,” for a padded protocol interface uses a reduced number of components by processing a narrower intermediate data stream, while at the same time multiplying the clock speed of its intermediate input and output so that it processes more data per clock cycle. The data streams can be narrowed to any integer factor of the original width (other than the original width).

    摘要翻译: 用于填充协议接口的数据转换器或“变速箱”通过处理较窄的中间数据流来减少数量的组件,同时将其中间输入和输出的时钟速度乘以使其处理更多的数据 时钟周期。 数据流可以缩小为原始宽度(原始宽度除外)的任何整数因子。

    Digital phase locked loop circuitry and methods
    5.
    发明授权
    Digital phase locked loop circuitry and methods 有权
    数字锁相环电路及方法

    公开(公告)号:US07869553B1

    公开(公告)日:2011-01-11

    申请号:US10923129

    申请日:2004-08-20

    IPC分类号: H03D3/24

    摘要: Phase locked loop circuitry operates digitally, to at least a large extent, to select from a plurality of phase-distributed candidate clock signals the signal that is closest in phase to transitions in another signal such as a clock data recovery (“CDR”) signal. The circuitry is constructed and operated to avoid glitches in the output clock signal that might otherwise result from changes in selection of the candidate clock signal. Frequency division of the candidate clock signals may be used to help the circuitry support serial communication at bit rates below frequencies that an analog portion of the phase locked loop circuitry can economically provide. Over-transmission or over-sampling may be used on the transmit side for similar reasons.

    摘要翻译: 锁相环电路以数字方式进行数字操作,至少在很大程度上从多个相位分布的候选时钟信号中选择最接近相位的信号,以便在诸如时钟数据恢复(“CDR”)信号的另一个信号中转换 。 该电路被构造和操作以避免由于候选时钟信号的选择变化而导致的输出时钟信号中的毛刺。 候选时钟信号的分频可以用于帮助电路以低于锁相环电路的模拟部分可以经济地提供的频率的比特率来支持串行通信。 出于同样的原因,发射侧可能会使用过量传输或过采样。

    Circuitry for providing configurable running disparity enforcement in 8B/10B encoding and error detection
    6.
    发明授权
    Circuitry for providing configurable running disparity enforcement in 8B/10B encoding and error detection 有权
    用于在8B / 10B编码和错误检测中提供可配置的运行视差执行的电路

    公开(公告)号:US07259699B1

    公开(公告)日:2007-08-21

    申请号:US11285944

    申请日:2005-11-23

    申请人: Ning Xue Chong H Lee

    发明人: Ning Xue Chong H Lee

    IPC分类号: H03M7/00

    CPC分类号: H03M5/145

    摘要: An integrated circuit like a programmable logic device (“PLD”) includes a communication channel employing 8B/10B coding. Disparity information determined by 8B/10B decoder circuitry in the communication channel is supplied to other circuitry of the PLD so that any requirement for disparity to have a particular value in conjunction with certain received codes can be checked. On the transmitter side, circuitry is provided for selectively forcing the 8B/10B encoder to use a commanded disparity (which can be either positive or negative) under particular circumstances.

    摘要翻译: 诸如可编程逻辑器件(“PLD”)的集成电路包括采用8B / 10B编码的通信信道。 在通信信道中由8B / 10B解码器电路确定的视差信息被提供给PLD的其他电路,使得可以检查与特定接收码相结合具有特定值的差异的任何要求。 在发射机侧,提供电路用于在特定情况下选择性地强制8B / 10B编码器使用命令的差异(其可以是正的或负的)。

    Correlating high-speed serial interface data and FIFO status signals in programmable logic devices
    7.
    发明授权
    Correlating high-speed serial interface data and FIFO status signals in programmable logic devices 有权
    在可编程逻辑器件中关联高速串行接口数据和FIFO状态信号

    公开(公告)号:US07162553B1

    公开(公告)日:2007-01-09

    申请号:US10956684

    申请日:2004-10-01

    申请人: Ning Xue Chong H Lee

    发明人: Ning Xue Chong H Lee

    IPC分类号: G06F13/12 H03K19/0175

    CPC分类号: H03G1/0088 H03G1/0094

    摘要: Status signals that are generated by one or more FIFO buffers in a high-speed serial interface (“HSSI”) may be combined with transmitted data samples in order to correlate the status signals to the respective data samples. The combined data and status signals may be transmitted either to the subsequent stages of the HSSI datapath or directly to the PLD via a dedicated path with less latency. The combined data and status signals can be used to determine whether a data sample corresponds to a valid data sample or an idle sequence, thereby allowing a user to control the flow of data.

    摘要翻译: 由高速串行接口(“HSSI”)中的一个或多个FIFO缓冲器生成的状态信号可以与发送的数据样本组合,以便将状态信号与各个数据样本相关联。 组合的数据和状态信号可以被发送到HSSI数据路径的后续阶段,或者通过具有较小延迟的专用路径直接发送到PLD。 组合的数据和状态信号可用于确定数据样本是否对应于有效数据样本或空闲序列,从而允许用户控制数据流。

    Next generation 8B10B architecture
    8.
    发明授权
    Next generation 8B10B architecture 有权
    下一代8B10B架构

    公开(公告)号:US07436210B2

    公开(公告)日:2008-10-14

    申请号:US11655797

    申请日:2007-01-18

    IPC分类号: H03K19/173

    CPC分类号: G06F13/385

    摘要: Eight-bit ten-bit (8B10B) coding is provided in a hard intellectual property (IP) block with the capability of supporting a greater range of data rates (e.g., data rates less than, equal to, and greater than 3.125 Gbps). Each channel of high speed serial interface circuitry includes receiver circuitry having two 8B10B decoders and transmitter circuitry having two 8B10B encoders. The receiver and transmitter circuitry can be configured to operate in one of three modes of operation: cascade mode, dual channel mode, and single channel mode.

    摘要翻译: 在具有支持更大范围的数据速率(例如,数据速率小于等于并且大于3.125Gbps)的能力的硬知识产权(IP)块中提供八位十位(8B10B)编码。 高速串行接口电路的每个通道包括具有两个8B10B解码器和具有两个8B10B编码器的发射机电路的接收机电路。 接收器和发射器电路可以配置为在三种工作模式之一下工作:级联模式,双通道模式和单通道模式。

    Data converter with multiple conversions for padded-protocol interface
    9.
    发明授权
    Data converter with multiple conversions for padded-protocol interface 有权
    具有多个转换的数据转换器,用于填充协议接口

    公开(公告)号:US07151470B1

    公开(公告)日:2006-12-19

    申请号:US10969450

    申请日:2004-10-20

    IPC分类号: H03M7/00

    CPC分类号: H03M7/04

    摘要: A data converter, or “gearbox,” for a padded protocol interface can perform a number of different conversions—e.g., between 64 and 66 bits, between 24 and 26 bits, or between 48 and 50 bits. This is accomplished by clocking the gearbox at different clock speeds, all derived from the same master clock (which may be recovered from the data in a receiver embodiment) using programmable dividers that allow the user to select the clock speed. When the conversion is not that one with the maximum width for which the gearbox is designed, unused bits are ignored. The converter can also find padding bits, for alignment purposes, in data of different widths, again ignoring unused bits when the data are not the widest for which the converter is designed.

    摘要翻译: 用于填充协议接口的数据转换器或“变速箱”可以执行多个不同的转换,例如在64位和66位之间,在24位和26位之间,或在48位和50位之间。 这是通过使用可允许用户选择时钟速度的可编程分频器从不同时钟速度对齿轮箱进行计时的,这些时钟速度全部来自相同的主时钟(可以从接收机实施例中的数据恢复)。 当转换不是设计齿轮箱的最大宽度的转换时,未使用的位将被忽略。 转换器还可以在不同宽度的数据中找到用于对齐目的的填充位,当数据不是设计转换器的最宽时,再次忽略未使用的位。

    Programmable logic devices with multi-standard byte synchronization and channel alignment for communication
    10.
    发明授权
    Programmable logic devices with multi-standard byte synchronization and channel alignment for communication 有权
    可编程逻辑器件具有多标准字节同步和通道对齐通讯

    公开(公告)号:US07577166B2

    公开(公告)日:2009-08-18

    申请号:US11189209

    申请日:2005-07-26

    IPC分类号: H04J3/07

    摘要: A programmable logic device (“PLD”) includes communication interface circuitry that can support any of a wide range of communication protocols, including Packet Over Sonet (“POS-5”) and 8-bit/10-bit (“8B10B”) protocols. The interface circuitry includes various functional blocks that are at least partly hard-wired to perform particular types of functions, but that in at least many cases are also partly programmable to allow the basic functions to be adapted for various protocols. Routing of signals to, from, between, and/or around the various functional blocks is also preferably at least partly programmable to facilitate combining the functional blocks in various ways to support various protocols.

    摘要翻译: 可编程逻辑器件(“PLD”)包括通信接口电路,其可以支持任何广泛的通信协议,包括分组超声波(“POS-5”)和8位/ 10比特(“8B10B”)协议 。 接口电路包括至少部分硬连线以执行特定类型的功能的各种功能块,但是在至少许多情况下也可部分地可编程以允许基本功能适应各种协议。 对各种功能块之间,之间和/或周围的信号的路由也优选地至少可部分地可编程以便于以各种方式组合功能块来支持各种协议。