公开(公告)号：US09170952B1

公开(公告)日：2015-10-27

申请号：US13338707

申请日：2011-12-28

申请人： Divya Vijayaraghavan ,  Vinson Chan ,  Keith Duwel ,  Chong H. Lee

发明人： Divya Vijayaraghavan ,  Vinson Chan ,  Keith Duwel ,  Chong H. Lee

IPC分类号： G06F13/00 ,  G06F12/02 ,  G06F12/08 ,  G06F13/12 ,  G06F13/14 ,  G06F11/00 ,  H01L25/00 ,  H04J3/06

CPC分类号： G06F12/0862 ,  G06F13/00 ,  H03K19/17744

摘要： A configurable interface includes a transmitter module and a receiver module, each configured to operate according to at least three different interface standards. The configurable interface further includes an interface module configured to determine a physical medium attachment (PMA) standard of a PMA coupled to the configurable interface and activate at least one component of the configurable interface based on the PMA standard. In an arrangement, the device interface supports a CAUI-4 standard.

摘要翻译： 可配置接口包括发射器模块和接收器模块，每个发送器模块和接收器模块被配置为根据至少三个不同的接口标准进行操作。 所述可配置接口还包括接口模块，所述接口模块被配置为确定耦合到所述可配置接口的PMA的物理介质连接（PMA）标准，并基于所述PMA标准激活所述可配置接口的至少一个组件。 在这种安排中，设备接口支持CAUI-4标准。

公开(公告)号：US08989284B1

公开(公告)日：2015-03-24

申请号：US13175749

申请日：2011-07-01

申请人： Divya Vijayaraghavan ,  Chong H. Lee

发明人： Divya Vijayaraghavan ,  Chong H. Lee

IPC分类号： H04L27/00

CPC分类号： H04W52/0229 ,  H04W52/0235 ,  H04W52/028 ,  Y02D70/00

摘要： A method and system for transitioning a communication circuit to a low-power state are disclosed. Where a first device and a second device communicate over a communication link, the first device may initiate a transition from an active state to a low-power state to conserve energy. A symbol may be encoded by the first device in data and transmitted to the second device. The first device may deactivate one or more components when entering the low-power state. Additionally, responsive to receiving and decoding the symbol, the second device may deactivate one or more components when entering the low-power state. In this manner, energy consumption of one or more components can be reduced and a low-power state may be entered to conserve energy.

摘要翻译： 公开了一种将通信电路转换为低功率状态的方法和系统。 在第一设备和第二设备通过通信链路进行通信的情况下，第一设备可以发起从活动状态到低功率状态的转换以节省能量。 符号可以由数据中的第一设备编码并被发送到第二设备。 当进入低功率状态时，第一设备可以去激活一个或多个组件。 另外，响应于符号的接收和解码，第二设备可以在进入低功率状态时停用一个或多个组件。 以这种方式，可以减少一个或多个部件的能量消耗，并且可以输入低功率状态以节省能量。

公开(公告)号：US08630198B1

公开(公告)日：2014-01-14

申请号：US12983180

申请日：2010-12-31

申请人： Divya Vijayaraghavan ,  Gopi Krishnamurthy ,  Ning Xue ,  Chong H. Lee

发明人： Divya Vijayaraghavan ,  Gopi Krishnamurthy ,  Ning Xue ,  Chong H. Lee

IPC分类号： G01R31/08

CPC分类号： H04L25/03885 ,  H04B3/04 ,  H04B3/32 ,  H04L25/03343

摘要： One embodiment relates to an integrated circuit configured to perform dynamic transmit equalization of a bi-directional lane. The integrated circuit including an interface between the physical coding and media access control circuitry, and an equalization control circuit which is external to the physical coding circuitry and which is configured to perform the dynamic transmit equalization using said interface. Another embodiment relates to a transceiver circuit which includes physical coding circuitry and media access control circuitry. The transceiver circuit further includes an interface between the physical coding circuitry and the media access control circuitry and an equalization controller which is external to the physical coding circuitry and which is configured to perform dynamic transmit equalization using said interface. The interface is configured to provide transmit coefficient data in a time-multiplexed signal format from the media access control circuitry to the physical coding circuitry. Other embodiments, aspects, and features are also disclosed.

摘要翻译： 一个实施例涉及被配置为执行双向通道的动态发送均衡的集成电路。 该集成电路包括物理编码和媒体访问控制电路之间的接口，以及在物理编码电路外部的配置成使用所述接口执行动态发送均衡的均衡控制电路。 另一个实施例涉及一种包括物理编码电路和媒体访问控制电路的收发器电路。 收发器电路还包括物理编码电路和媒体访问控制电路之间的接口以及在物理编码电路之外的均衡控制器，并且被配置为使用所述接口执行动态发送均衡。 接口被配置为以时间复用的信号格式提供从媒体访问控制电路到物理编码电路的传输系数数据。 还公开了其它实施例，方面和特征。

公开(公告)号：US08477831B2

公开(公告)日：2013-07-02

申请号：US12860482

申请日：2010-08-20

申请人： Divya Vijayaraghavan ,  Chong H. Lee

发明人： Divya Vijayaraghavan ,  Chong H. Lee

IPC分类号： H04L27/06

CPC分类号： H04L5/1446 ,  H04L1/0002 ,  H04L1/0025

摘要： An interface for use in a local device includes a transmitter portion programmably configurable to at least three data rates, a receiver portion programmably configurable to those at least three data rates, and an automatic speed negotiation module operatively connected to the transmitter portion and the receiver portion to configure the transmitter portion and the receiver portion for communication with a remote device at a single data rate that is a best available one of those at least three data rates. The date rate can be adjusted by adjusting transmitter data path width and receiver data path width, adjusting a frequency of said transmitter data path and said receiver data path, and oversampling. Byte serialization or deserialization can be enabled or disabled to alter the width of the data, depending on the data rate, for transfer to/from the remainder of the local device.

摘要翻译： 用于本地设备的接口包括可编程地配置为至少三个数据速率的发射机部分，可编程地配置为至少三个数据速率的接收机部分，以及可操作地连接到发射机部分和接收机部分的自动速度协商模块 配置发射机部分和接收机部分，以与作为这些至少三个数据速率中最好的可用数据速率的单个数据速率与远程设备进行通信。 可以通过调整发射机数据路径宽度和接收机数据路径宽度，调整所述发射机数据路径和所述接收机数据路径的频率以及过采样来调整日期速率。 可以使能或禁用字节序列化或反序列化，以根据数据速率改变数据的宽度，以传输到/从本地设备的其余部分。

公开(公告)号：US20100277201A1

公开(公告)日：2010-11-04

申请号：US12434606

申请日：2009-05-01

申请人： Curt Wortman ,  Chong H. Lee ,  Richard G. Cliff

发明人： Curt Wortman ,  Chong H. Lee ,  Richard G. Cliff

IPC分类号： H03K19/173 ,  G06F17/50

CPC分类号： G06F17/5045 ,  G06F2217/84 ,  H03K19/17724 ,  H03K19/17732

摘要： An integrated circuit (IC) is provided. The IC includes a first region having an array of programmable logic cells. The IC also includes a second region incorporated into the IC and in communication with the first region. The second region includes standard logic cells and base cells. In one embodiment, the standard logic cells are assembled or interconnected to accommodate known protocols. The base cells include configurable logic to adapt to modifications to emerging communication protocols, which are supported by the base cells. The second region can be embedded in the first region in one embodiment. In another embodiment, the second region is defined around a perimeter of the first region. The configurable logic may be composed of hybrid logic elements that have metal mask programmable interconnections so that as emerging communication protocols evolve and are modified, the IC can be modified to accommodate to the changes in the protocol. In another embodiment, a generic device can be customized by replacing the original function with a completely new function targeting a specific application space, e.g., replacing the original function such as a PCI Express, used for computing based applications, with 40 G/100 G Ethernet and Interlaken, used in wireline applications. A method of designing an integrated circuit is also provided.

摘要翻译： 提供集成电路（IC）。 IC包括具有可编程逻辑单元阵列的第一区域。 IC还包括结合到IC中并与第一区域通信的第二区域。 第二区包括标准逻辑单元和基本单元。 在一个实施例中，标准逻辑单元被组合或互连以适应已知协议。 基本单元包括可配置逻辑以适应由基本单元支持的新兴通信协议的修改。 在一个实施例中，第二区域可以嵌入第一区域。 在另一个实施例中，第二区域围绕第一区域的周边限定。 可配置逻辑可以由具有金属掩模可编程互连的混合逻辑元件组成，使得随着新兴通信协议的发展和修改，可以修改IC以适应协议的改变。 在另一个实施例中，可以通过用针对特定应用空间的全新功能替换原始功能来定制通用设备，例如用40G / 100G替换用于基于计算的应用的诸如PCI Express的原始功能 以太网和因特拉肯，用于有线应用。 还提供了一种设计集成电路的方法。

公开(公告)号：US20100215086A1

公开(公告)日：2010-08-26

申请号：US12288178

申请日：2008-10-17

申请人： Divya Vijayaraghavan ,  Curt Wortman ,  Chong H. Lee

发明人： Divya Vijayaraghavan ,  Curt Wortman ,  Chong H. Lee

IPC分类号： H04B1/38

CPC分类号： H04B1/005 ,  G06F13/385 ,  H04L69/12 ,  H04L69/18

摘要： Embodiments in the disclosure include a multi-protocol transceiver including a configurable arrangement of receive and/or transmit circuitry. An exemplary transceiver can be selectively configured to effectively transmit and/or receive data communications corresponding to a select one of a plurality of high-speed communication protocols. Another more particular embodiment disclosed includes a configurable data path through link-wide Physical Coding Sub-layer (“PCS”) circuitry including link-wide clock compensation, encoding/decoding, and scrambling/descrambling circuitry and lane striping/de-striping circuitry; the configurable data path further includes lane-wide circuitry including clock compensation, encoding/decoding, receive block sync, and Physical Medium Access sub-layer (“PMA”) circuitry, and further includes bit muxing/de-muxing circuitry coupled to Physical Medium Dependent (“PMD”) sub-layer circuitry.

摘要翻译： 本公开的实施例包括包括接收和/或发送电路的可配置布置的多协议收发器。 可以选择性地配置示例性收发器以有效地发送和/或接收对应于多个高速通信协议中的选择一个的数据通信。 所公开的另一更具体的实施例包括通过链路范围物理编码子层（“PCS”）电路的可配置数据路径，包括链路范围时钟补偿，编码/解码以及加扰/解扰频电路和通道条带/去条纹电路; 可配置数据路径还包括通道宽电路，包括时钟补偿，编码/解码，接收块同步和物理介质访问子层（“PMA”）电路，并且还包括耦合到物理介质的位复用/解复用电路 从属（“PMD”）子层电路。

公开(公告)号：US07675326B1

公开(公告)日：2010-03-09

申请号：US12163709

申请日：2008-06-27

申请人： Mei Luo ,  Sergey Shumarayev ,  Wilson Wong ,  Chong H. Lee

发明人： Mei Luo ,  Sergey Shumarayev ,  Wilson Wong ,  Chong H. Lee

IPC分类号： H03K19/094

CPC分类号： H03K19/00369 ,  H03K19/01812 ,  H03K19/01837 ,  H03K19/018514 ,  H03K19/018585

摘要： Systems and methods are provided using dynamically adjustable differential output drivers. Integrated circuits such as programmable logic devices may be provided with adjustable differential output drivers for transmitting high-speed data to other integrated circuits. The peak-to-peak output voltage and common-mode voltage of the output drivers may be adjusted. Dynamic control circuitry may be used to control the settings of current sources, programmable resistors, and voltage source circuitry in the adjustable differential output driver automatically in real time. The adjustable components in the differential output driver may be adjusted by the dynamic control circuitry based on feedback information received from the integrated circuit to which the data is transmitted.

摘要翻译： 使用动态可调差分输出驱动器提供系统和方法。 诸如可编程逻辑器件的集成电路可以设置有用于将高速数据传输到其他集成电路的可调差分输出驱动器。 可以调整输出驱动器的峰峰值输出电压和共模电压。 动态控制电路可用于实时自动控制可调差分输出驱动器中的电流源，可编程电阻和电压源电路的设置。 基于从发送数据的集成电路接收到的反馈信息，可以通过动态控制电路来调整差分输出驱动器中的可调节部件。

公开(公告)号：US07616657B2

公开(公告)日：2009-11-10

申请号：US11402417

申请日：2006-04-11

申请人： Sergey Shumarayev ,  Bill W Bereza ,  Chong H Lee ,  Rakesh H Patel ,  Wilson Wong

发明人： Sergey Shumarayev ,  Bill W Bereza ,  Chong H Lee ,  Rakesh H Patel ,  Wilson Wong

IPC分类号： H04J3/00

CPC分类号： H04L5/14 ,  H03K19/17744 ,  H04L27/00

摘要： High-speed serial data transceiver circuitry on a programmable logic device (“PLD”) includes some channels that are able to operate at data rates up to a first, relatively low maximum data rate, and other channels that are able to operate at data rates up to a second, relatively high maximum data rate. The relatively low-speed channels are served by relatively low-speed phase locked loop (“PLL”) circuitry, and have other circuit components that are typically needed for handling data that is transmitted at relatively low data rates. The relatively high-speed channels are served by relatively high-speed PLLs, and have other circuit components that are typically needed for handling data that is transmitted at relatively high data rates.

摘要翻译： 可编程逻辑器件（“PLD”）上的高速串行数据收发器电路包括一些能够以高达第一，相对较低的最大数据速率的数据速率工作的通道，以及能够以数据速率操作的其他通道 达到第二个相对较高的最大数据速率。 相对低速的通道由相对低速的锁相环（“PLL”）电路服务，并且具有通常用于处理以相对低的数据速率发送的数据所需的其他电路组件。 相对高速的信道由相对高速的PLL服务，并且具有通常用于处理以相对高的数据速率传输的数据所需的其他电路部件。

公开(公告)号：US07386767B1

公开(公告)日：2008-06-10

申请号：US10958447

申请日：2004-10-05

申请人： Ning Xue ,  Chong H Lee

发明人： Ning Xue ,  Chong H Lee

IPC分类号： G06F11/00

CPC分类号： G06F11/0772 ,  G06F11/076

摘要： A programmable bit error rate monitor includes an error counter, a monitoring period counter with a programmable upper bound to set the monitoring period, and an error flag generator that compares the actual error count to a programmable threshold. The error flag generator may generate flags at different sensitivity levels, and the user may programmably select one of those flags. The three flags can be generated by independent comparators, or they can be extrapolated from the base error flag—e.g., by comparing only certain bits of the error count to corresponding bits of the threshold.

摘要翻译： 可编程误码率监视器包括错误计数器，具有可编程上限的监视周期计数器以设置监视周期，以及将实际错误计数与可编程阈值进行比较的错误标志发生器。 错误标志生成器可以生成不同灵敏度级别的标志，并且用户可以可编程地选择这些标志之一。 这三个标志可以由独立的比较器产生，或者它们可以从基本错误标志中外推，例如通过仅将错误计数的某些位与阈值的相应位进行比较。

公开(公告)号：US07199732B1

公开(公告)日：2007-04-03

申请号：US11139083

申请日：2005-05-26

申请人： Ning Xue ,  Chong H Lee

发明人： Ning Xue ,  Chong H Lee

IPC分类号： H03M7/00

CPC分类号： H04L25/4908

摘要： A data converter, or “gearbox,” for a padded protocol interface uses a reduced number of components by processing a narrower intermediate data stream, while at the same time multiplying the clock speed of its intermediate input and output so that it processes more data per clock cycle. The data streams can be narrowed to any integer factor of the original width (other than the original width).

摘要翻译： 用于填充协议接口的数据转换器或“变速箱”通过处理较窄的中间数据流来减少数量的组件，同时将其中间输入和输出的时钟速度乘以使其处理更多的数据 时钟周期。 数据流可以缩小为原始宽度（原始宽度除外）的任何整数因子。