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13 条记录 (耗时 0.013 秒)

    Semiconductor integrated circuit and control method
    2.
    发明授权
    Semiconductor integrated circuit and control method 有权
    半导体集成电路及控制方法

    公开(公告)号：US08665626B2

    公开(公告)日：2014-03-04

    申请号：US13235539

    申请日：2011-09-19

    申请人： Akira Yazawa ,  Tomohiro Iwashita

    发明人： Akira Yazawa ,  Tomohiro Iwashita

    IPC分类号： G11C17/00

    CPC分类号： G11C29/785 ,  G11C17/16 ,  G11C29/80

    摘要： A semiconductor integrated circuit for selecting one from a plurality of external storage devices and loading an execution program that includes a fuse part having a plurality of internal fuse circuits, and a processing unit that loads the execution program from the external storage device selected according to a value indicated by the internal fuse circuit.

    摘要翻译： 一种半导体集成电路，用于从多个外部存储装置中选择一个并加载包括具有多个内部熔丝电路的熔丝部分的执行程序，以及处理单元，该处理单元从根据 值由内部熔丝回路指示。

    Method for smelting copper sulfide concentrate
    3.
    发明授权
    Method for smelting copper sulfide concentrate 有权
    冶炼硫化铜精矿的方法

    公开(公告)号：US06416565B1

    公开(公告)日：2002-07-09

    申请号：US09555020

    申请日：2000-10-05

    申请人： Akira Yazawa ,  Yoichi Takeda ,  Nozomu Hasegawa ,  Yoshiaki Mori

    发明人： Akira Yazawa ,  Yoichi Takeda ,  Nozomu Hasegawa ,  Yoshiaki Mori

    IPC分类号： C22B1500

    CPC分类号： C22B15/0054 ,  C22B15/0028 ,  C22B15/0047 ,  C22B15/006

    摘要： A method of oxygen-smelting copper sulfide concentrate to obtain white metal, nearly white metal matte or blister copper by removing most of the Fe in the copper sulfide concentrate into the slag as well as removing part or most of the S therein as SO2 wherein oxygen-smelting is carried out to produce; slag in which a weight ratio of CaO to (SiO2+CaO) is 0.3 to 0.6 and a weight ratio of Fe to (FeOx+SiO2+CaO) is 0.2 to 0.5, and white metal, nearly white metal matte or blister copper, by adding SiO2 material and CaO material to the copper sulfide concentrate as flux.

    摘要翻译： 通过将硫化铜精矿中的大部分Fe去除到炉渣中以及将其中的部分或大部分S除去为SO 2，得到白色金属，接近白色金属锍或起泡铜的方法，其中氧气 - 进行生产; CaO与（SiO2 + CaO）的重量比为0.3〜0.6，Fe与（FeOx + SiO2 + CaO）的重量比为0.2〜0.5的矿渣，白色金属，近白色金属无光泽或起泡铜，由 将SiO2材料和CaO材料作为助熔剂加入到硫化铜精矿中。

    Watchdog timer circuit suited for use in microcomputer
    4.
    发明授权
    Watchdog timer circuit suited for use in microcomputer 失效
    看门狗定时器电路适用于微机

    公开(公告)号：US4879647A

    公开(公告)日：1989-11-07

    申请号：US873020

    申请日：1986-06-11

    申请人： Akira Yazawa

    发明人： Akira Yazawa

    IPC分类号： G06F11/30 ,  G06F1/24 ,  G06F11/00 ,  H03K5/13 ,  H03K17/22 ,  H03K17/28

    CPC分类号： G06F11/0757 ,  H03K17/22 ,  G06F11/1441

    摘要： A watchdog timer circuit employed in a microcomputer is disclosed. The watchdog timer circuit detects the occurrence of a program abnormal termination or an infinite loop operation and includes a capacitor, a charging circuit charging the capacitor when a predetermined instruction is executed, a discharging circuit discharging the capacitor when other instructions are executed, a detection circuit detecting the voltage across the capacitor and producing a detection signal when the voltage across the capacitor becomes smaller than a reference voltage, and a reset circuit resets the microcomputer to its initial state in response to an abnormal detection circuit. When the program termination or an infinite loop operation occurs, the predetermined instruction is not executed for a long period of time. The capacitor continues to be discharged. As a result, the detection signal is produced. The microcomputer is thereby reset to its initial state.

    摘要翻译： 公开了一种在微计算机中采用的看门狗定时器电路。 看门狗定时器电路检测到程序异常终止或无限循环操作的发生，并且包括电容器，当执行预定指令时对电容器充电的充电电路，当执行其它指令时放电电容器的放电电路;检测电路 检测电容器两端的电压，并且当电容器两端的电压变得小于参考电压时产生检测信号，并且复位电路响应于异常检测电路将微计算机复位到初始状态。 当程序终止或无限循环操作发生时，预定指令不长时间执行。 电容器继续放电。 结果，产生检测信号。 微型计算机因此被复位到其初始状态。

    Counter having a plurality of cascaded flip-flops
    6.
    发明授权
    Counter having a plurality of cascaded flip-flops 失效
    计数器具有多个级联的触发器

    公开(公告)号：US4493095A

    公开(公告)日：1985-01-08

    申请号：US378356

    申请日：1982-05-14

    申请人： Akira Yazawa

    发明人： Akira Yazawa

    IPC分类号： H03K21/38 ,  H03K23/00 ,  H03K23/58 ,  H03K23/66 ,  H03K21/32 ,  H03K21/34

    CPC分类号： H03K21/38 ,  H03K23/58

    摘要： An improved counter wherein consecutively cascaded flip-flops of the prior art are divided into two groups. A first detector produces a first signal in response to a predetermined set of flip-flop states of the first group. A second detector produces a second signal in response to a predetermined set of flip-flop states of the second group. A third detector produces a count output in response to simultaneous existence of the first and second signals. The output from the first group is arranged in phase so that the second signal may be produced before the count output is produced, by applying an inverted output of the first group to the input of the second group.

    摘要翻译： 一种改进的计数器，其中先有技术的连续级联的触发器被分成两组。 第一检测器响应于第一组的预定触发器状态集合产生第一信号。 第二检测器响应于第二组的预定触发器状态集合产生第二信号。 第三检测器响应于同时存在第一和第二信号而产生计数输出。 来自第一组的输出被同相布置，使得可以在产生计数输出之前产生第二信号，通过将第一组的反相输出应用于第二组的输入。

    Noise shaping circuit having plural feedback coefficient multipliers
    7.
    发明授权
    Noise shaping circuit having plural feedback coefficient multipliers 失效
    具有多个反馈系数乘法器的噪声整形电路

    公开(公告)号：US5278559A

    公开(公告)日：1994-01-11

    申请号：US914318

    申请日：1992-07-17

    申请人： Akira Yazawa

    发明人： Akira Yazawa

    IPC分类号： H03M3/00 ,  H03M3/02

    CPC分类号： H03M3/448 ,  H03M3/454

    摘要： Coefficient multipliers are inserted into feedback loops between an output of a delay unit and an input of an adder, and between an output of the other delay unit and the other input of the adder. Here, it is assumed that an input data supplied to an integration circuit is X(z), an output data supplied from the integration circuit is A(z), and an output data of a quantizer is Y(z). Then, the following equations are met.Y(z)=X(z)+Q(1-Z.sup.-1).sup.2 (1-.alpha.Z.sup.-1)where .alpha. is a coefficient of the coefficient multipliers.A(z)={X(z)+Y(z).multidot.F(z)-Y(z)}/F(z)F(z)=(1K.sub.1 Z.sup.-1) (1-K.sub.2 Z.sup.-1) . . . (1-K.sub.n Z.sup.-1)where K.sub.1 to K.sub.n are coefficients of real numbers meeting the relation 0

    摘要翻译： 系数乘法器插入到延迟单元的输出和加法器的输入之间以及另一个延迟单元的输出和加法器的另一个输入之间的反馈回路中。 这里，假设提供给积分电路的输入数据为X（z），从积分电路输出的输出数据为A（z），量化器的输出数据为Y（z）。 然后，满足以下等式。 Y（z）= X（z）+ Q（1-Z-1）2（1-（α）Z-1）其中（α）是系数乘数的系数。 A（z）=（X（z）+ Y（z）* F（z）-Y（z））/ F（z）F（z）=（1K1Z-1） 。 。 。 （1-Kn Z-1）其中K1至Kn是满足关系0

    Circuit for designating write and read address to provide a delay time in a sound system
    8.
    发明授权
    Circuit for designating write and read address to provide a delay time in a sound system 失效
    用于指定写入和读取地址以在音响系统中提供延迟时间的电路

    公开(公告)号：US5657466A

    公开(公告)日：1997-08-12

    申请号：US703929

    申请日：1996-08-28

    申请人： Akira Yazawa

    发明人： Akira Yazawa

    IPC分类号： G11C8/00 ,  G06F5/06 ,  G06F12/02 ,  G10K15/12 ,  G11C8/04 ,  G06F12/06

    CPC分类号： G06F5/065 ,  G11C8/04

    摘要： A write address and a read address are generated by use of a pointer register and a single register set common to the write and read addresses. The read register is obtained by an addition or subtraction of a pointer value and a value selected from offset values of the register set, and the write register is obtained by adding one to the read address or subtracting one therefrom.

    摘要翻译： 通过使用指针寄存器和写入和读取地址共同的单个寄存器来生成写入地址和读取地址。 读取寄存器是通过加上或减去指针值和从寄存器组的偏移值中选择的值来获得的，并且通过将一个加到读取地址或从中减去一个来获得写入寄存器。

    SEMICONDUCTOR INTEGRATED CIRCUIT AND CONTROL METHOD
    9.
    发明申请
    SEMICONDUCTOR INTEGRATED CIRCUIT AND CONTROL METHOD 有权
    半导体集成电路和控制方法

    公开(公告)号：US20120069690A1

    公开(公告)日：2012-03-22

    申请号：US13235539

    申请日：2011-09-19

    申请人： Akira YAZAWA ,  Tomohiro IWASHITA

    发明人： Akira YAZAWA ,  Tomohiro IWASHITA

    IPC分类号： G11C29/04 ,  G11C17/16

    CPC分类号： G11C29/785 ,  G11C17/16 ,  G11C29/80

    摘要： A semiconductor integrated circuit for selecting one from a plurality of external storage devices and loading an execution program that includes a fuse part having a plurality of internal fuse circuits, and a processing unit that loads the execution program from the external storage device selected according to a value indicated by the internal fuse circuit.

    摘要翻译： 一种半导体集成电路，用于从多个外部存储装置中选择一个并加载包括具有多个内部熔丝电路的熔丝部分的执行程序，以及处理单元，该处理单元从根据 值由内部熔丝回路指示。