公开(公告)号：US07787453B2

公开(公告)日：2010-08-31

申请号：US11882550

申请日：2007-08-02

申请人： Thanh Tran ,  Andrew Hwang ,  Henry Chou

发明人： Thanh Tran ,  Andrew Hwang ,  Henry Chou

IPC分类号： H04L12/28

CPC分类号： H04L45/302 ,  H04L45/745 ,  H04L49/351 ,  H04L49/90 ,  H04L69/161

摘要： The present invention is directed to methods and systems for scaling receive protocol processing by allowing the network load from a network adapter to be balanced across multiple CPUs based on RSS and/or QoS traffic classification techniques.

摘要翻译： 本发明涉及用于通过基于RSS和/或QoS流量分类技术允许来自网络适配器的网络负载在多个CPU之间平衡来缩放接收协议处理的方法和系统。

公开(公告)号：US20070223519A1

公开(公告)日：2007-09-27

申请号：US11476846

申请日：2006-06-29

申请人： Wei Wang ,  Andrew Hwang ,  Thanh Tran

发明人： Wei Wang ,  Andrew Hwang ,  Thanh Tran

IPC分类号： H04L12/66

CPC分类号： G06F1/08 ,  G06F21/81 ,  G06F21/85

摘要： In Gigibit Ethernet Systems, the Trusted Platform Module (TPM) is designed to provide trust and security to a platform through integrity measurement, protected storage, and other cryptographic functions. The present invention relates to a TPM-LAN chip with separate TPM and LAN power management. The TPM-LAN chip is designed such a way that power is reduced significantly in different power management modes compared to the legacy devices. This is accomplished by turning off certain clocks during certain operating modes.

摘要翻译： 在Gigibit以太网系统中，可信平台模块（TPM）旨在通过完整性测量，受保护存储和其他加密功能为平台提供信任和安全性。 本发明涉及具有单独的TPM和LAN功率管理的TPM-LAN芯片。 TPM-LAN芯片的设计使得与传统设备相比，功率在不同的电源管理模式下显着降低。 这是通过在某些操作模式下关闭某些时钟来实现的。

公开(公告)号：US20060143344A1

公开(公告)日：2006-06-29

申请号：US11357637

申请日：2006-02-16

申请人： Steven Lindsay ,  Andrew Hwang ,  Andrew Naylor ,  Michael Asker

发明人： Steven Lindsay ,  Andrew Hwang ,  Andrew Naylor ,  Michael Asker

IPC分类号： G06F13/42

CPC分类号： H04L29/06 ,  G06F1/263 ,  G06F1/30 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3287 ,  H04L12/12 ,  H04L41/0213 ,  H04L41/06 ,  H04L41/08 ,  H04L41/0803 ,  H04L41/082 ,  H04L41/0856 ,  H04L41/0869 ,  H04L41/147 ,  H04L69/18 ,  H04L69/22 ,  H04L69/40 ,  Y02D10/126 ,  Y02D10/171 ,  Y02D50/40 ,  Y02D50/42

摘要： A network controller having a multiprotocol bus interface adapter coupled between a communication network and a computer bus, the adapter including a predictive time base generator; and a management bus controller adapted to monitor and manage preselected components coupled with one of the communication network and the computer bus. The management bus controller is adapted to employ an Alert Standard Format (ASF) specification protocol, a System Management Bus (SMBus) specification protocol, an Intelligent Platform Management Interface (IPMI) specification protocol, a Simple Network Management Protocol (SNMP), or a combination thereof. The network controller also includes a 10/100/1000BASE-T IEEE Std. 802.3-compliant transceiver and media access controller coupled with the communication network; a buffer memory coupled with the MAC, wherein the buffer memory includes one of a packet buffer memory, a frame buffer memory, a queue memory, and a combination thereof; and a transmit CPU and a receive CPU coupled with the multiprotocol bus interface adapter and the management bus controller. The network controller can be a single-chip VLSI device in an 0.18 micron CMOS VLSI implementation.

公开(公告)号：US20050060587A1

公开(公告)日：2005-03-17

申请号：US10887068

申请日：2004-07-08

申请人： Andrew Hwang ,  Augustine Kuo ,  Michael Hurt

发明人： Andrew Hwang ,  Augustine Kuo ,  Michael Hurt

IPC分类号： G06F1/28 ,  G06F1/26

CPC分类号： G06F1/28

摘要： Certain aspects of a system for controlling power for a network interface controller device may comprise a precision voltage comparator that may instantaneously detect ramp up of a main voltage corresponding to a main voltage source in order to control the network interface controller device. A power monitor may detect when a threshold voltage of the main voltage is reached during the ramp up. A main voltage source switch and an auxiliary voltage source switch may switch an output from an auxiliary voltage to the main voltage source without the switches being simultaneously on. The power monitor may determine whether the main voltage is ramping up in excess of a determined rate and if so, may decrease a rate at which the main voltage ramps up. A current limiter and/or the power monitor may monitor and limit an inrush current caused during main voltage ramp up.

摘要翻译： 用于控制网络接口控制器设备的电源的系统的某些方面可以包括精密电压比较器，其可以瞬时检测对应于主电压源的主电压的上升以便控制网络接口控制器设备。 功率监视器可以在升高期间检测何时达到主电压的阈值电压。 主电压源开关和辅助电压源开关可以将辅助电压的输出切换到主电压源，而不会同时打开开关。 功率监视器可以确定主电压是否正在上升超过确定的速率，如果是，则可以降低主电压上升的速率。 电流限制器和/或功率监视器可以监视和限制在主电压升高期间引起的浪涌电流。

公开(公告)号：US08102842B2

公开(公告)日：2012-01-24

申请号：US11832440

申请日：2007-08-01

申请人： Thanh Tran ,  Henry Chou ,  Scott Denton ,  Andrew Hwang

发明人： Thanh Tran ,  Henry Chou ,  Scott Denton ,  Andrew Hwang

IPC分类号： H04L12/50

CPC分类号： H04L49/352

摘要： Switching between communication ports of a notebook is typically accomplished using an off-chip local area network (LAN) switch or an off-chip high speed analog multiplexer. This off-chip component is disadvantageous for several reasons, including: added cost of an additional component; increased overall power consumption because transmit amplitude loss; and reduced cable reach and link performance due to hybrid mismatch and signal distortions. To reduce cost and preserve electrical and networking performance, an integrated switch is provided to multiplex signals of a networking communication chip to multiple network paths.

摘要翻译： 笔记本的通信端口之间的切换通常使用片外局域网（LAN）开关或片外高速模拟多路复用器来完成。 这种片外组件由于以下几个原因是不利的，其中包括：附加组件的附加成本; 增加总功耗，因为传输幅度损失; 并且由于混合不匹配和信号失真而降低了电缆距离和链路性能。 为了降低成本并保持电气和网络性能，提供集成开关以将网络通信芯片的信号复用到多个网络路径。

公开(公告)号：US20050060621A1

公开(公告)日：2005-03-17

申请号：US10940146

申请日：2004-09-13

申请人： Jonathan Lee ,  Xiaogang Zhu ,  Andrew Hwang

发明人： Jonathan Lee ,  Xiaogang Zhu ,  Andrew Hwang

IPC分类号： G11C29/48 ,  G11C29/00

CPC分类号： G11C29/48 ,  G11C2029/0401

摘要： Aspects of the invention may be found in a method and system for testing an integrated circuit and may comprise an address selector, data selector and staging register coupled to a signal generator. The address selector may comprise a direct access memory test (DAMT) mode address control input and one or more output address pins coupled to an embedded memory device under test (DUT). The data selector may be coupled to at least one data pin and control pin of the signal generator and may comprise a DAMT mode data control input and at least one data output coupled to embedded memory DUT. A staging register comprising a first output clock rate which is one-quarter (¼) its input clock rate and matches a DUT burst write frequency may be coupled to an input of the data selector. A DAMT mode control may configure the memory DUT for DAMT operation.

摘要翻译： 可以在用于测试集成电路的方法和系统中找到本发明的方面，并且可以包括地址选择器，数据选择器和耦合到信号发生器的分级寄存器。 地址选择器可以包括直接访问存储器测试（DAMT）模式地址控制输入和耦合到被测嵌入式存储器件（DUT）的一个或多个输出地址引脚。 数据选择器可以耦合到信号发生器的至少一个数据引脚和控制引脚，并且可以包括DAMT模式数据控制输入和耦合到嵌入式存储器DUT的至少一个数据输出。 包括其输入时钟速率四分之一（¼）的第一输出时钟速率并与DUT突发写入频率匹配的分级寄存器可以耦合到数据选择器的输入端。 DAMT模式控制可以配置用于DAMT操作的存储器DUT。

公开(公告)号：US08397091B2

公开(公告)日：2013-03-12

申请号：US11476846

申请日：2006-06-29

申请人： Wei Wang ,  Andrew Hwang ,  Thanh Tran

发明人： Wei Wang ,  Andrew Hwang ,  Thanh Tran

IPC分类号： G06F1/32

CPC分类号： G06F1/08 ,  G06F21/81 ,  G06F21/85

摘要： In Gigabit Ethernet Systems, the Trusted Platform Module (TPM) is designed to provide trust and security to a platform through integrity measurement, protected storage, and other cryptographic functions. The present invention relates to a TPM-LAN chip with separate TPM and LAN power management. The TPM-LAN chip is designed such a way that power is reduced significantly in different power management modes compared to the legacy devices. This is accomplished by turning off certain clocks during certain operating modes.

摘要翻译： 在千兆以太网系统中，可信平台模块（TPM）旨在通过完整性测量，受保护存储和其他加密功能为平台提供信任和安全性。 本发明涉及具有单独的TPM和LAN功率管理的TPM-LAN芯片。 TPM-LAN芯片的设计使得与传统设备相比，功率在不同的电源管理模式下显着降低。 这是通过在某些操作模式下关闭某些时钟来实现的。

公开(公告)号：US20080034101A1

公开(公告)日：2008-02-07

申请号：US11882550

申请日：2007-08-02

申请人： Thanh Tran ,  Andrew Hwang ,  Henry Chou

发明人： Thanh Tran ,  Andrew Hwang ,  Henry Chou

IPC分类号： G06F15/173

CPC分类号： H04L45/302 ,  H04L45/745 ,  H04L49/351 ,  H04L49/90 ,  H04L69/161

摘要： The present invention is directed to methods and systems for scaling receive protocol processing by allowing the network load from a network adapter to be balanced across multiple CPUs based on RSS and/or QoS traffic classification techniques.

摘要翻译： 本发明涉及用于通过基于RSS和/或QoS流量分类技术允许来自网络适配器的网络负载在多个CPU之间平衡来缩放接收协议处理的方法和系统。

公开(公告)号：US08498291B2

公开(公告)日：2013-07-30

申请号：US13327036

申请日：2011-12-15

申请人： Thanh Tran ,  Henry Chou ,  Scott Denton ,  Andrew Hwang

发明人： Thanh Tran ,  Henry Chou ,  Scott Denton ,  Andrew Hwang

IPC分类号： H04L12/50 ,  H04Q11/00

CPC分类号： H04L49/352

摘要： Switching between communication ports of a notebook is typically accomplished using an off-chip local area network (LAN) switch or an off-chip high speed analog multiplexer. This off-chip component is disadvantageous for several reasons, including: added cost of an additional component; increased overall power consumption because transmit amplitude loss; and reduced cable reach and link performance due to hybrid mismatch and signal distortions. To reduce cost and preserve electrical and networking performance, an integrated switch is provided to multiplex signals of a networking communication chip to multiple network paths.

摘要翻译： 笔记本的通信端口之间的切换通常使用片外局域网（LAN）开关或片外高速模拟多路复用器来完成。 这种片外组件由于以下几个原因是不利的，其中包括：附加组件的附加成本; 增加总功耗，因为传输幅度损失; 并且由于混合不匹配和信号失真而降低了电缆距离和链路性能。 为了降低成本并保持电气和网络性能，提供集成开关以将网络通信芯片的信号复用到多个网络路径。

公开(公告)号：US20120087249A1

公开(公告)日：2012-04-12

申请号：US13327036

申请日：2011-12-15

申请人： Thanh TRAN ,  Henry CHOU ,  Scott DENTON ,  Andrew HWANG

发明人： Thanh TRAN ,  Henry CHOU ,  Scott DENTON ,  Andrew HWANG

IPC分类号： H04L12/26

CPC分类号： H04L49/352

摘要： Switching between communication ports of a notebook is typically accomplished using an off-chip local area network (LAN) switch or an off-chip high speed analog multiplexer. This off-chip component is disadvantageous for several reasons, including: added cost of an additional component; increased overall power consumption because transmit amplitude loss; and reduced cable reach and link performance due to hybrid mismatch and signal distortions. To reduce cost and preserve electrical and networking performance, an integrated switch is provided to multiplex signals of a networking communication chip to multiple network paths.

摘要翻译： 笔记本的通信端口之间的切换通常使用片外局域网（LAN）开关或片外高速模拟多路复用器来完成。 这种片外组件由于以下几个原因是不利的，其中包括：附加组件的附加成本; 增加总功耗，因为传输幅度损失; 并且由于混合不匹配和信号失真而降低了电缆距离和链路性能。 为了降低成本并保持电气和网络性能，提供集成开关以将网络通信芯片的信号复用到多个网络路径。