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公开(公告)号:US5284781A
公开(公告)日:1994-02-08
申请号:US54489
申请日:1993-04-30
IPC分类号: H01L21/208 , H01L33/00 , H01L21/265
CPC分类号: H01L33/0008 , H01L21/02395 , H01L21/02463 , H01L21/02546 , H01L21/02576 , H01L21/02625 , H01L21/02658 , H01L33/0062
摘要: A liquid phase epitaxial (LPE) melt is formed to be oversaturated with gallium arsenide, and to have a first temperature. A surface of a gallium arsenide substrate is converted to a first P-type layer (12). Subsequently, the first P-type layer (12) and the substrate (11) are covered with the LPE melt. A N-type layer (13) is formed on the first P-type layer (12) by reducing the first temperature of the LPE melt to a second temperature. A second P-type layer (14) is formed on the N-type layer (13) by reducing the second temperature of the LPE melt to a third temperature.
摘要翻译: 形成液相外延(LPE)熔体以使其与砷化镓过饱和并具有第一温度。 砷化镓衬底的表面被转换成第一P型层(12)。 随后,用LPE熔体覆盖第一P型层(12)和衬底(11)。 通过将LPE熔体的第一温度降低到第二温度,在第一P型层(12)上形成N型层(13)。 通过将LPE熔体的第二温度降低到第三温度,在N型层(13)上形成第二P型层(14)。
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公开(公告)号:US5223079A
公开(公告)日:1993-06-29
申请号:US670555
申请日:1991-03-18
IPC分类号: C30B19/00 , C30B19/06 , H01L21/208
CPC分类号: C30B19/00 , C30B19/063 , C30B29/42 , H01L21/02546 , H01L21/02576 , H01L21/02625 , H01L21/02628 , Y10S148/101
摘要: A thin layer of liquid phase epitaxial melt material (26) is formed on a wafer (15,16). The thin melt layer (26) is held in contact with the wafer (15,16) while the temperature of the thin melt layer (26) and the wafer (15,16) are reduced to crystallize a portion of the melt material thereby producing thin and accurately controlled epitaxial layers on the wafer (15,16).
摘要翻译: 在晶片(15,16)上形成薄层的液相外延熔融材料(26)。 薄熔体层(26)与晶片(15,16)保持接触,而薄熔体层(26)和晶片(15,16)的温度被降低以使熔融材料的一部分结晶,从而产生 薄且精确控制的外延层在晶片(15,16)上。
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3.
公开(公告)号:US4714518A
公开(公告)日:1987-12-22
申请号:US3317
申请日:1987-01-14
IPC分类号: H01L21/283 , H01L21/285 , H01L21/311 , H01L21/314 , H01L21/318 , H01L33/00 , B44C1/22
CPC分类号: H01L21/314 , H01L21/28575 , H01L21/31116 , H01L21/3185
摘要: A method for providing a dual layer diffusion mask or encapsulation coating for use with III-V compound semiconductors, the dual layer coating comprising an inner layer of silicon which closely matches the coefficient of thermal expansion of the III-V compound semiconductor and an outer layer of silicon nitride which is relatively impermeable to subsequent metallization and for thereafter applying metallized contacts to the III-V compound semiconductor through selectively etched openings in the diffusion mask or encapsulation coating.
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