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19 条记录 (耗时 0.019 秒)

    MEMORY CONTROL COMPONENT WITH SPLIT AUXILIARY CHANNEL
    1.
    发明公开
    MEMORY CONTROL COMPONENT WITH SPLIT AUXILIARY CHANNEL 审中-公开

    公开(公告)号：US20240143437A1

    公开(公告)日：2024-05-02

    申请号：US17976994

    申请日：2022-10-31

    申请人： Astera Labs, Inc.

    发明人： Anh T. Tran ,  Dhairya Bapodra ,  Nirav Ishwarbhai Patel

    IPC分类号： G06F3/06

    CPC分类号： G06F3/0613 ,  G06F3/0629 ,  G06F3/0659 ,  G06F3/0673

    摘要： A memory control component allocates a portion of an auxiliary signaling channel and corresponding memory storage, conventionally dedicated to error correction code (ECC) conveyance and storage, for conveyance of metadata and/or other types of component-level information—splitting the auxiliary channel between metadata and ECC conveyance/storage in proportions that obviate conventional metadata conveyance/storage via the primary data channel and thus maintaining full primary channel bandwidth/storage-capacity for user data.

    CXL HDM decoding sequencing for reduced area and power consumption
    3.
    发明授权
    CXL HDM decoding sequencing for reduced area and power consumption 有权

    公开(公告)号：US12067266B1

    公开(公告)日：2024-08-20

    申请号：US17867106

    申请日：2022-07-18

    申请人： Astera Labs, Inc.

    发明人： Enrique Musoll ,  Anh Thien Tran

    IPC分类号： G06F3/06 ,  G06F1/3234

    CPC分类号： G06F3/0625 ,  G06F1/3275 ,  G06F3/0655 ,  G06F3/0679

    摘要： A total number V of virtual host-managed device memory (HDM) decoder configurations are generated for the same total number V of HDM memory regions attached to a non-host computing device. Each virtual HDM decoder configuration in the virtual HDM decoder configurations corresponds to a respective HDM memory region in the HDM memory regions. A proper subset of one or more virtual HDM decoder configurations is selected from among the virtual HDM decoder configurations to configure one or more physical HDM decoders of a total number P of the non-host computing device into one or more virtual HDM decoders. The one or more physical HDM decoders configured as one or more virtual HDM decoders are applied to translate a host physical address (HPA) received from a host computing device in a memory access transaction involving the host computing device and the non-host computing device.

    SSD-Form-Factor Memory-Expansion Cartridge with Field-Replaceable DRAM Modules
    8.
    发明公开
    SSD-Form-Factor Memory-Expansion Cartridge with Field-Replaceable DRAM Modules 审中-公开

    公开(公告)号：US20240329854A1

    公开(公告)日：2024-10-03

    申请号：US18127643

    申请日：2023-03-28

    申请人： Astera Labs, Inc.

    发明人： Avinash R. Sharma

    IPC分类号： G06F3/06

    CPC分类号： G06F3/0619 ,  G06F3/0653 ,  G06F3/0673

    摘要： A hot-swappable DRAM cartridge implemented in a standards-compliant SSD form-factor has an access panel that opens to enable removal and insertion of socketed DRAM memory modules. In at least some implementations, the DRAM cartridge complies with form-factor, protocol, connector, and pin-out/signal specifications set forth in one or more Enterprise and Data Center Standard Form Factor (EDSFF) specifications promulgated by Storage Networking Industry Association (SNIA) including, for example and without limitation, form-factor specifications set forth in EDSFF standards E3.S, E3.S 2T, E3.L and E3.L 2T.

    Retimer with mesochronous intra-lane path controllers
    9.
    发明授权
    Retimer with mesochronous intra-lane path controllers 有权

    公开(公告)号：US12003610B1

    公开(公告)日：2024-06-04

    申请号：US17724207

    申请日：2022-04-19

    申请人： Astera Labs, Inc.

    发明人： Enrique Musoll ,  Casey Morrison ,  Ken (Keqin) Han ,  Pulkit Khandelwal ,  Subbarao Arumilli

    IPC分类号： H04L7/04 ,  G06F13/42 ,  H04L7/00

    CPC分类号： H04L7/0041 ,  G06F13/4291 ,  G06F2213/0026

    摘要： First and second clock signals are generated based on signal transitions within first and second streams of symbols, respectively, received within an integrated circuit component, the first and second clock signals having a time-varying phase offset with respect to one another. A first control circuit, operating in a first timing domain established by the first clock signal, generates first control information based on the first stream of symbols and forwards the first control information, via a domain crossing circuit that bridges the time-varying phase offset, to a second control circuit operating in a second timing domain. The second control circuit generates a third stream of symbols based on the first control information and on the second stream of symbols, and a transmit circuit outputs the third stream of symbols from the integrated circuit component synchronously with respect to the second clock signal.