公开(公告)号：US20100053412A1

公开(公告)日：2010-03-04

申请号：US12461908

申请日：2009-08-27

申请人： Yoshihiro Sekimoto ,  Atsushi Semi

发明人： Yoshihiro Sekimoto ,  Atsushi Semi

IPC分类号： G03B13/32 ,  H04N5/225 ,  G03B9/08

CPC分类号： G03B9/08 ,  H04N5/2251 ,  H04N5/2257 ,  H04N5/23212

摘要： A camera module 1 of the present invention includes a moving magnet type mechanical shutter 2 and a lens unit 3 (lens drive section) for driving a lens by electromagnetic force. A magnetic field for driving the lens is set so that a light path is closed by a shutter fin while a magnetic field leaked from the lens unit 3 is acting on a drive mechanism of the mechanical shutter 2. With the configuration, the leak magnetic field leaked from the lens unit 3 causes the light path to be closed at a faster speed by the shutter fin of the mechanical shutter 2. Accordingly, generation of a smear can be prevented by the camera module including the lens drive section and the moving magnet type mechanical shutter, which are driven by the electromagnetic force.

摘要翻译： 本发明的照相机模块1包括用于通过电磁力驱动透镜的移动磁体式机械快门2和透镜单元3（透镜驱动部）。 设置用于驱动透镜的磁场，使得在从透镜单元3泄漏的磁场作用在机械快门2的驱动机构上时，通过快门翅片关闭光路。通过该结构，泄漏磁场 从透镜单元3泄漏的光路通过机械快门2的快门翅片以更快的速度闭合。因此，可以通过包括透镜驱动部和移动磁体型的相机模块来防止污迹的产生 机械快门，由电磁力驱动。

公开(公告)号：US06487124B2

公开(公告)日：2002-11-26

申请号：US09955016

申请日：2001-09-19

申请人： Atsushi Semi

发明人： Atsushi Semi

IPC分类号： G11C1606

CPC分类号： G11C16/24

摘要： A selected memory cell is correctly read even when a threshold value of a non-selected memory cell that shares a word line is low. When reading a memory cell MC12, a discharge transistor select circuit 47 selectively discharges a bit line BL2 connected to the memory cell MC12 and two bit lines BL0 and BL1 that are adjacent to the bit line BL2. A precharge control circuit 46 fixes to a precharge voltage a center bit line among five bit lines that include a bit line BL3 connected to the memory cell MC12 and four bit lines that are adjacent to the bit line BL3 and brings the remaining bit lines into a floating state with the precharge voltage. Thus, the potential of the bit line BL3 is prevented from being lowered as a consequence of a leak current occurring via the non-selected memory cell MC when the threshold value of the selected memory cell MC12 is high, by which the erroneous determination that the ON-state is provided is prevented from being made.

公开(公告)号：US08107006B2

公开(公告)日：2012-01-31

申请号：US12461908

申请日：2009-08-27

申请人： Yoshihiro Sekimoto ,  Atsushi Semi

发明人： Yoshihiro Sekimoto ,  Atsushi Semi

IPC分类号： H04N9/64 ,  H04N5/232 ,  H04N5/225 ,  G03B13/00

CPC分类号： G03B9/08 ,  H04N5/2251 ,  H04N5/2257 ,  H04N5/23212

摘要： A camera module 1 of the present invention includes a moving magnet type mechanical shutter 2 and a lens unit 3 (lens drive section) for driving a lens by electromagnetic force. A magnetic field for driving the lens is set so that a light path is closed by a shutter fin while a magnetic field leaked from the lens unit 3 is acting on a drive mechanism of the mechanical shutter 2. With the configuration, the leak magnetic field leaked from the lens unit 3 causes the light path to be closed at a faster speed by the shutter fin of the mechanical shutter 2. Accordingly, generation of a smear can be prevented by the camera module including the lens drive section and the moving magnet type mechanical shutter, which are driven by the electromagnetic force.

摘要翻译： 本发明的照相机模块1包括用于通过电磁力驱动透镜的移动磁体式机械快门2和透镜单元3（透镜驱动部）。 设置用于驱动透镜的磁场，使得在从透镜单元3泄漏的磁场作用在机械快门2的驱动机构上时，通过快门翅片关闭光路。通过该结构，泄漏磁场 从透镜单元3泄漏的光路通过机械快门2的快门翅片以更快的速度闭合。因此，可以通过包括透镜驱动部和移动磁体型的相机模块来防止污迹的产生 机械快门，由电磁力驱动。

公开(公告)号：US5821783A

公开(公告)日：1998-10-13

申请号：US778695

申请日：1997-01-03

申请人： Yasuo Torimaru ,  Atsushi Semi ,  Kaneo Kawaishi

发明人： Yasuo Torimaru ,  Atsushi Semi ,  Kaneo Kawaishi

IPC分类号： H03K17/12 ,  H03K17/687 ,  H03K19/003 ,  H03K19/0175 ,  H03K19/0185 ,  H03K19/0948 ,  H03B1/00

CPC分类号： H03K19/00361 ,  H03K19/018521

摘要： A buffer circuit according to the present invention includes an input terminal for inputting an input signal, an inverter circuit for inverting the input signal and outputting the inverted input signal to an output terminal, wherein the inverter circuit has a plurality of PMOS transistors and a plurality of NMOS transistors; each of the plurality of PMOS transistors has a source connected to a power source, a drain connected to the output terminal, and a gate connected to the input terminal; each of the plurality of NMOS transistors has a source connected to a ground, a drain connected to the output terminal, and a gate connected to the input terminal; and the gate of at least one of the plurality of PMOS transistors and NMOS transistors is connected to the input terminal via a fuse element which can be selectively disconnected.

摘要翻译： 根据本发明的缓冲电路包括用于输入输入信号的输入端子，用于反相输入信号并将反相输入信号输出到输出端的反相器电路，其中反相器电路具有多个PMOS晶体管和多个PMOS晶体管 的NMOS晶体管; 多个PMOS晶体管中的每一个具有连接到电源的源极，连接到输出端子的漏极和连接到输入端子的栅极; 多个NMOS晶体管中的每一个具有连接到地的源极，连接到输出端子的漏极和连接到输入端子的栅极; 并且多个PMOS晶体管和NMOS晶体管中的至少一个的栅极经由可选择性地断开的熔丝元件连接到输入端。

公开(公告)号：US06847124B2

公开(公告)日：2005-01-25

申请号：US10452907

申请日：2003-06-03

申请人： Atsushi Semi

发明人： Atsushi Semi

IPC分类号： H01L23/52 ,  H01L21/3205 ,  H01L21/60 ,  H01L23/485 ,  H01L29/40

CPC分类号： H01L24/05 ,  H01L24/03 ,  H01L2224/02166 ,  H01L2224/05093 ,  H01L2224/05095 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/00

摘要： A semiconductor device includes: a semiconductor substrate; a bonding pad having an interconnection region that provides for an external electrical contact; a first interlayer insulating layer interposed between the semiconductor substrate and the bonding pad; and a metal wiring layer that is embedded in the first interlayer insulating layer. The metal wiring layer is made of a softer material than that of the first interlayer insulating layer. The metal wiring layer at least partially overlaps with the interconnection region in the stacked direction of the layers, and the area of metal wiring layer overlapping with the interconnection region includes notches that extend through the metal wiring layer in the stacked direction and separate the metal wiring layer in the layer direction. Portions of the first interlayer insulating layer are embedded in the notches. This enables the size of the semiconductor device to be reduced by efficiently utilizing the underlying layers of the bonding pad while preventing cracking in these layers.

摘要翻译： 半导体器件包括：半导体衬底; 具有提供外部电接触的互连区域的焊盘; 介于所述半导体衬底和所述焊盘之间的第一层间绝缘层; 以及嵌入在所述第一层间绝缘层中的金属布线层。 金属布线层由比第一层间绝缘层更软的材料制成。 金属布线层在层叠方向上与互连区域至少部分地重叠，并且与配线区域重叠的金属布线层的面积包括在堆叠方向上延伸穿过金属布线层的凹槽，并且将金属布线 层在层方向。 第一层间绝缘层的一部分嵌入凹口中。 这使得能够通过有效地利用接合焊盘的下层来减小半导体器件的尺寸，同时防止这些层中的开裂。

公开(公告)号：US5327376A

公开(公告)日：1994-07-05

申请号：US25368

申请日：1993-02-24

申请人： Atsushi Semi

发明人： Atsushi Semi

IPC分类号： G11C11/412 ,  H03K3/037 ,  B11C13/00

CPC分类号： G11C11/412 ,  H03K3/0375

摘要： A static memory cell is connected to a first bit line and a second bit line, and includes the following: a first inverter section having a first input and a first output; a second inverter section having a second input connected to a first output through a first node, and a second output connected to the first input through a second node; a first switching section for allowing or not allowing conduction between the first bit line and the first node; a first capacitor arranged between the second bit line and the first node; a second switching section for allowing or not allowing conduction between the second bit line and the second node; and a second capacitor arranged between the first bit line and the second node.

摘要翻译： 静态存储单元连接到第一位线和第二位线，并且包括以下：第一反相器部分，具有第一输入和第一输出; 第二逆变器部分，具有通过第一节点连接到第一输出的第二输入和通过第二节点连接到第一输入的第二输出; 用于允许或不允许第一位线和第一节点之间的导通的第一开关部分; 布置在第二位线和第一节点之间的第一电容器; 第二切换部，用于允许或不允许第二位线和第二节点之间的导通; 以及布置在第一位线和第二节点之间的第二电容器。

公开(公告)号：US5875139A

公开(公告)日：1999-02-23

申请号：US886342

申请日：1997-07-01

申请人： Atsushi Semi

发明人： Atsushi Semi

IPC分类号： G11C11/41 ,  G11C7/12 ,  G11C7/00

CPC分类号： G11C7/12

摘要： According to the present invention, a bitline precharge circuit for a semiconductor memory device is provided. The semiconductor memory device includes: a plurality of word lines arranged in a row direction; a plurality of bitlines forming a plurality of bitline pairs arranged in a column direction; and a plurality of memory cells connected between each of the plurality of bitline pairs via a plurality of switching elements, the switching elements being controlled by respectively different ones of the word lines. The bitline precharge circuit charges a potential on all of the bitlines to a precharge level which is approximately intermediate between a power supply voltage and a ground voltage before a write operation or a read operation is performed and is characterized by including a write precharge circuit for further varying the potential on the bitlines, which has been charged to the precharge level, by a predetermined level before the write operation is performed.

摘要翻译： 根据本发明，提供了一种用于半导体存储器件的位线预充电电路。 半导体存储器件包括：排列成行方向的多个字线; 多个位线，形成沿列方向布置的多个位线对; 以及经由多个开关元件连接在所述多个位线对中的每一个之间的多个存储单元，所述开关元件由分别不同的字线控制。 位线预充电电路将所有位线上的电位充电到在执行写入操作或读取操作之前大约在电源电压和接地电压之间的中间的预充电电平，并且其特征在于包括用于进一步的写入预充电电路 在执行写入操作之前将已经被充电到预充电电平的位线上的电位改变预定电平。