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    NONVOLATILE MEMORY DEVICE AND WORDLINE DRIVING METHOD THEREOF
    1.
    发明申请
    NONVOLATILE MEMORY DEVICE AND WORDLINE DRIVING METHOD THEREOF 审中-公开
    非易失性存储器件及其驱动方法

    公开(公告)号：US20160365149A1

    公开(公告)日：2016-12-15

    申请号：US15172929

    申请日：2016-06-03

    申请人： SANG-WAN NAM ,  Sun-Min Yun ,  Bongsoon Lim ,  Yoon-Hee Choi

    发明人： SANG-WAN NAM ,  Sun-Min Yun ,  Bongsoon Lim ,  Yoon-Hee Choi

    IPC分类号： G11C16/08 ,  G11C16/34 ,  G11C16/28 ,  G11C16/04 ,  G11C16/10

    CPC分类号： G11C16/08 ,  G11C8/08 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/28 ,  G11C16/3459

    摘要： According to example embodiments of inventive concepts, a nonvolatile memory device includes a memory cell array, an address decoder, an input/output circuit, a voltage generation circuit, and control logic. The memory cell array includes a plurality of memory blocks on a substrate. Each of the memory blocks includes a plurality of strings connected between bit lines and a common source line. The address decoder is configured to measure impedance information of word lines of a selected memory block. The voltage generation circuit is configured to generate word line voltages to be applied to word lines, and at least one of the word line voltages includes an offset voltage and a target voltage. The control logic is configured to adjust a level of the offset voltage and the offset time depending on the measured impedance information of the word lines.

    摘要翻译： 根据发明构思的示例实施例，非易失性存储器件包括存储单元阵列，地址解码器，输入/输出电路，电压产生电路和控制逻辑。 存储单元阵列包括在衬底上的多个存储块。 每个存储块包括连接在位线和公共源极线之间的多个串。 地址解码器被配置为测量所选择的存储器块的字线的阻抗信息。 电压产生电路被配置为产生要施加到字线的字线电压，并且字线电压中的至少一个包括偏移电压和目标电压。 控制逻辑被配置为根据测得的字线的阻抗信息来调整偏移电压和偏移时间的电平。

    Nonvolatile memory device and storage device including nonvolatile memory device
    2.
    发明授权
    Nonvolatile memory device and storage device including nonvolatile memory device 有权

    公开(公告)号：US10658040B2

    公开(公告)日：2020-05-19

    申请号：US15351550

    申请日：2016-11-15

    申请人： Bongsoon Lim ,  Jung-Yun Yun ,  Ji-Suk Kim ,  Sang-Won Park

    发明人： Bongsoon Lim ,  Jung-Yun Yun ,  Ji-Suk Kim ,  Sang-Won Park

    IPC分类号： G11C16/10 ,  G11C16/34 ,  G11C16/26 ,  G11C16/08

    摘要： A storage device includes a nonvolatile memory device and a controller. The controller provides the nonvolatile memory device with first data, an address, and a program start command and provides the nonvolatile memory device with second data after the program start command is provided the nonvolatile memory device. The nonvolatile memory device is configured to initiate a program operation, which is based on the first data, in response to the program start command and to continue to perform, based on the first data and the second data, the program operation when the second data is provided to the nonvolatile memory device. The nonvolatile memory device is configured to perform a program and a verification read of a first program loop based on the first data, the verification read of the first program loop being performed using one verification voltage.

    NONVOLATILE MEMORY DEVICE AND WORLDLINE DRIVING METHOD THEREOF
    3.
    发明申请
    NONVOLATILE MEMORY DEVICE AND WORLDLINE DRIVING METHOD THEREOF 有权
    非易失性存储器件及其驱动方法

    公开(公告)号：US20160035423A1

    公开(公告)日：2016-02-04

    申请号：US14741224

    申请日：2015-06-16

    申请人： Sang-Wan NAM ,  Sun-Min YUN ,  Bongsoon LIM ,  Yoon-Hee CHOI

    发明人： Sang-Wan NAM ,  Sun-Min YUN ,  Bongsoon LIM ,  Yoon-Hee CHOI

    IPC分类号： G11C16/08 ,  G11C16/10 ,  G11C16/28 ,  G11C16/04

    CPC分类号： G11C16/08 ,  G11C8/08 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/28 ,  G11C16/3459

    摘要： According to example embodiments of inventive concepts, a nonvolatile memory device includes a memory cell array, an address decoder, an input/output circuit, a voltage generation circuit, and control logic. The memory cell array includes a plurality of memory blocks on a substrate. Each of the memory blocks includes a plurality of strings connected between bit lines and a common source line. The address decoder is configured to measure impedance information of word lines of a selected memory block. The voltage generation circuit is configured to generate word line voltages to be applied to word lines, and at least one of the word line voltages includes an offset voltage and a target voltage. The control logic is configured to adjust a level of the offset voltage and the offset time depending on the measured impedance information of the word lines.

    摘要翻译： 根据发明构思的示例实施例，非易失性存储器件包括存储单元阵列，地址解码器，输入/输出电路，电压产生电路和控制逻辑。 存储单元阵列包括在衬底上的多个存储块。 每个存储块包括连接在位线和公共源极线之间的多个串。 地址解码器被配置为测量所选择的存储器块的字线的阻抗信息。 电压产生电路被配置为产生要施加到字线的字线电压，并且字线电压中的至少一个包括偏移电压和目标电压。 控制逻辑被配置为根据测得的字线的阻抗信息来调整偏移电压和偏移时间的电平。