公开(公告)号：US08977637B2

公开(公告)日：2015-03-10

申请号：US13599600

申请日：2012-08-30

申请人： Sameh Asaad ,  Bernard V. Brezzo ,  Donna N Eng Dillenberger ,  Parijat Dube ,  Balakrishna Raghavendra Iyer ,  Hong Min ,  Bharat Sukhwani ,  Mathew S. Thoennes

发明人： Sameh Asaad ,  Bernard V. Brezzo ,  Donna N Eng Dillenberger ,  Parijat Dube ,  Balakrishna Raghavendra Iyer ,  Hong Min ,  Bharat Sukhwani ,  Mathew S. Thoennes

IPC分类号： G06F17/30

CPC分类号： G06F17/30 ,  G06F17/30289 ,  G06F17/30442

摘要： Methods and arrangements for facilitating accelerations of database functions. A field programmable gate array is incorporated. At least one query control block is incorporated in the field programmable gate array, and database management system operations are accelerated via the field programmable gate array. The accelerating includes employing the at least one query control block to execute a query without reconfiguring the field programmable gate array.

摘要翻译： 促进数据库功能加速的方法和安排。 并入现场可编程门阵列。 现场可编程门阵列中至少包含一个查询控制块，通过现场可编程门阵列加速数据库管理系统的运行。 加速包括采用至少一个查询控制块来执行查询而不重新配置现场可编程门阵列。

公开(公告)号：US20140067845A1

公开(公告)日：2014-03-06

申请号：US13599600

申请日：2012-08-30

申请人： Sameh Asaad ,  Bernard V. Brezzo ,  Donna N. Eng Dillenberger ,  Parijat Dube ,  Balakrishna Raghavendra Iyer ,  Hong Min ,  Bharat Sukhwani ,  Mathew S. Thoennes

发明人： Sameh Asaad ,  Bernard V. Brezzo ,  Donna N. Eng Dillenberger ,  Parijat Dube ,  Balakrishna Raghavendra Iyer ,  Hong Min ,  Bharat Sukhwani ,  Mathew S. Thoennes

IPC分类号： G06F17/30

CPC分类号： G06F17/30 ,  G06F17/30289 ,  G06F17/30442

摘要： Methods and arrangements for facilitating accelerations of database functions. A field programmable gate array is incorporated. At least one query control block is incorporated in the field programmable gate array, and database management system operations are accelerated via the field programmable gate array. The accelerating includes employing the at least one query control block to execute a query without reconfiguring the field programmable gate array.

公开(公告)号：US20120259804A1

公开(公告)日：2012-10-11

申请号：US13083414

申请日：2011-04-08

申请人： Bernard V. Brezzo ,  Leland Chang ,  Steven K. Esser ,  Daniel J. Friedman ,  Yong Liu ,  Dharmendra S. Modha ,  Robert K. Montoye ,  Bipin Rajendran ,  Jae-sun Seo ,  Jose A. Tierno

发明人： Bernard V. Brezzo ,  Leland Chang ,  Steven K. Esser ,  Daniel J. Friedman ,  Yong Liu ,  Dharmendra S. Modha ,  Robert K. Montoye ,  Bipin Rajendran ,  Jae-sun Seo ,  Jose A. Tierno

IPC分类号： G06N3/04 ,  G06N3/08

CPC分类号： G06N3/063 ,  G06N3/04 ,  G06N3/049 ,  G06N3/082

摘要： A reconfigurable neural network circuit is provided. The reconfigurable neural network circuit comprises an electronic synapse array including multiple synapses interconnecting a plurality of digital electronic neurons. Each neuron comprises an integrator that integrates input spikes and generates a signal when the integrated inputs exceed a threshold. The circuit further comprises a control module for reconfiguring the synapse array. The control module comprises a global final state machine that controls timing for operation of the circuit, and a priority encoder that allows spiking neurons to sequentially access the synapse array.

公开(公告)号：US20140067851A1

公开(公告)日：2014-03-06

申请号：US13616639

申请日：2012-09-14

申请人： Sameh Asaad ,  Bernard V. Brezzo ,  Donna N. Eng Dillenberger ,  Parijat Dube ,  Balakrishna Raghavendra Iyer ,  Hong Min ,  Bharat Sukhwani ,  Mathew S. Thoennes

发明人： Sameh Asaad ,  Bernard V. Brezzo ,  Donna N. Eng Dillenberger ,  Parijat Dube ,  Balakrishna Raghavendra Iyer ,  Hong Min ,  Bharat Sukhwani ,  Mathew S. Thoennes

IPC分类号： G06F17/30

CPC分类号： G06F17/30 ,  G06F17/30289 ,  G06F17/30442

摘要： Methods and arrangements for facilitating accelerations of database functions. A field programmable gate array is incorporated. At least one query control block is incorporated in the field programmable gate array, and database management system operations are accelerated via the field programmable gate array. The accelerating includes employing the at least one query control block to execute a query without reconfiguring the field programmable gate array.

摘要翻译： 促进数据库功能加速的方法和安排。 并入现场可编程门阵列。 现场可编程门阵列中至少包含一个查询控制块，通过现场可编程门阵列加速数据库管理系统的运行。 加速包括采用至少一个查询控制块来执行查询而不重新配置现场可编程门阵列。

公开(公告)号：US08983992B2

公开(公告)日：2015-03-17

申请号：US13616639

申请日：2012-09-14

申请人： Sameh Asaad ,  Bernard V. Brezzo ,  Donna N Eng Dillenberger ,  Parijat Dube ,  Balakrishna Raghavendra Iyer ,  Hong Min ,  Bharat Sukhwani ,  Mathew S. Thoennes

发明人： Sameh Asaad ,  Bernard V. Brezzo ,  Donna N Eng Dillenberger ,  Parijat Dube ,  Balakrishna Raghavendra Iyer ,  Hong Min ,  Bharat Sukhwani ,  Mathew S. Thoennes

IPC分类号： G06F17/30

CPC分类号： G06F17/30 ,  G06F17/30289 ,  G06F17/30442

摘要： Methods and arrangements for facilitating accelerations of database functions. A field programmable gate array is incorporated. At least one query control block is incorporated in the field programmable gate array, and database management system operations are accelerated via the field programmable gate array. The accelerating includes employing the at least one query control block to execute a query without reconfiguring the field programmable gate array.

公开(公告)号：US08898097B2

公开(公告)日：2014-11-25

申请号：US13587594

申请日：2012-08-16

申请人： Bernard V. Brezzo ,  Leland Chang ,  Steven K. Esser ,  Daniel J. Friedman ,  Yong Liu ,  Dharmendra S. Modha ,  Robert K. Montoye ,  Bipin Rajendran ,  Jae-sun Seo ,  Jose A. Tierno

发明人： Bernard V. Brezzo ,  Leland Chang ,  Steven K. Esser ,  Daniel J. Friedman ,  Yong Liu ,  Dharmendra S. Modha ,  Robert K. Montoye ,  Bipin Rajendran ,  Jae-sun Seo ,  Jose A. Tierno

IPC分类号： G06N3/063 ,  G06N3/04

CPC分类号： G06N3/063 ,  G06N3/04 ,  G06N3/049 ,  G06N3/082

摘要： A reconfigurable neural network circuit is provided. The reconfigurable neural network circuit comprises an electronic synapse array including multiple synapses interconnecting a plurality of digital electronic neurons. Each neuron comprises an integrator that integrates input spikes and generates a signal when the integrated inputs exceed a threshold. The circuit further comprises a control module for reconfiguring the synapse array. The control module comprises a global final state machine that controls timing for operation of the circuit, and a priority encoder that allows spiking neurons to sequentially access the synapse array.

摘要翻译： 提供可重构神经网络电路。 可重构神经网络电路包括电子突触阵列，其包括互连多个数字电子神经元的多个突触。 每个神经元包括积分器，其对输入尖峰进行积分，并且当集成输入超过阈值时产生信号。 电路还包括用于重新配置突触阵列的控制模块。 控制模块包括控制电路操作的定时的全局最终状态机，以及允许加标神经元依次访问突触阵列的优先编码器。

公开(公告)号：US08856055B2

公开(公告)日：2014-10-07

申请号：US13083414

申请日：2011-04-08

申请人： Bernard V. Brezzo ,  Leland Chang ,  Steven K. Esser ,  Daniel J. Friedman ,  Yong Liu ,  Dharmendra S. Modha ,  Robert K. Montoye ,  Bipin Rajendran ,  Jae-sun Seo ,  Jose A. Tierno

发明人： Bernard V. Brezzo ,  Leland Chang ,  Steven K. Esser ,  Daniel J. Friedman ,  Yong Liu ,  Dharmendra S. Modha ,  Robert K. Montoye ,  Bipin Rajendran ,  Jae-sun Seo ,  Jose A. Tierno

IPC分类号： G06N3/063 ,  G06N3/04

CPC分类号： G06N3/063 ,  G06N3/04 ,  G06N3/049 ,  G06N3/082

摘要： A reconfigurable neural network circuit is provided. The reconfigurable neural network circuit comprises an electronic synapse array including multiple synapses interconnecting a plurality of digital electronic neurons. Each neuron comprises an integrator that integrates input spikes and generates a signal when the integrated inputs exceed a threshold. The circuit further comprises a control module for reconfiguring the synapse array. The control module comprises a global final state machine that controls timing for operation of the circuit, and a priority encoder that allows spiking neurons to sequentially access the synapse array.

公开(公告)号：US08737233B2

公开(公告)日：2014-05-27

申请号：US13236109

申请日：2011-09-19

申请人： Sameh Asaad ,  Bernard V. Brezzo ,  Mohit Kapur

发明人： Sameh Asaad ,  Bernard V. Brezzo ,  Mohit Kapur

IPC分类号： H04L12/26 ,  H04L12/28 ,  H04L12/16 ,  H04L12/66

CPC分类号： H04L12/2602 ,  G06F13/4059 ,  H04L12/28 ,  H04L12/66 ,  H04L43/00

摘要： Techniques are disclosed for increasing the throughput of a multiplexed electrical bus by exploiting available pipeline stages of a computer or other system. For example, a method for increasing a throughput of an electrical bus that connects at least two devices in a system comprises introducing at least one signal hold stage in a signal-receiving one of the two devices, such that a maximum frequency at which the two devices are operated is not limited by a number of cycles of an operating frequency of the electrical bus needed for a signal to propagate from a signal-transmitting one of the two devices to the signal-receiving one of the two devices. Preferably, the signal hold stage introduced in the signal-receiving one of the two devices is a pipeline stage re-allocated from the signal-transmitting one of the two devices.

摘要翻译： 公开了通过利用计算机或其他系统的可用流水线级来增加多路复用电母线的吞吐量的技术。 例如，用于增加连接系统中的至少两个设备的电气总线的吞吐量的方法包括在两个设备中的一个信号接收中引入至少一个信号保持级，使得两个 操作设备不受信号从两个设备中的信号传输一个传播到两个设备中的信号接收设备之一所需的电气总线的工作频率的周期数量的限制。 优选地，引入到两个装置中的信号接收装置之一中的信号保持级是从两个装置中的信号发送装置之一重新分配的流水线级。

公开(公告)号：US20130070606A1

公开(公告)日：2013-03-21

申请号：US13236109

申请日：2011-09-19

申请人： Sameh Asaad ,  Bernard V. Brezzo ,  Mohit Kapur

发明人： Sameh Asaad ,  Bernard V. Brezzo ,  Mohit Kapur

IPC分类号： H04L12/66 ,  H04L12/26

CPC分类号： H04L12/2602 ,  G06F13/4059 ,  H04L12/28 ,  H04L12/66 ,  H04L43/00

摘要： Techniques are disclosed for increasing the throughput of a multiplexed electrical bus by exploiting available pipeline stages of a computer or other system. For example, a method for increasing a throughput of an electrical bus that connects at least two devices in a system comprises introducing at least one signal hold stage in a signal-receiving one of the two devices, such that a maximum frequency at which the two devices are operated is not limited by a number of cycles of an operating frequency of the electrical bus needed for a signal to propagate from a signal-transmitting one of the two devices to the signal-receiving one of the two devices. Preferably, the signal hold stage introduced in the signal-receiving one of the two devices is a pipeline stage re-allocated from the signal-transmitting one of the two devices.

摘要翻译： 公开了通过利用计算机或其他系统的可用流水线级来增加多路复用电母线的吞吐量的技术。 例如，用于增加连接系统中的至少两个设备的电气总线的吞吐量的方法包括在两个设备中的一个信号接收中引入至少一个信号保持级，使得两个 操作设备不受信号从两个设备中的信号传输一个传播到两个设备中的信号接收设备之一所需的电气总线的工作频率的周期数量的限制。 优选地，引入到两个装置中的信号接收装置之一中的信号保持级是从两个装置中的信号发送装置之一重新分配的流水线级。

公开(公告)号：US20120317062A1

公开(公告)日：2012-12-13

申请号：US13587594

申请日：2012-08-16

申请人： Bernard V. BREZZO ,  Leland Chang ,  Steven K. Esser ,  Daniel J. Friedman ,  Yong Liu ,  Dharmendra S. Modha ,  Robert K. Montoye ,  Bipin Rajendran ,  Jae-sun Seo ,  Jose A. Tierno

发明人： Bernard V. BREZZO ,  Leland Chang ,  Steven K. Esser ,  Daniel J. Friedman ,  Yong Liu ,  Dharmendra S. Modha ,  Robert K. Montoye ,  Bipin Rajendran ,  Jae-sun Seo ,  Jose A. Tierno

IPC分类号： G06N3/08

CPC分类号： G06N3/063 ,  G06N3/04 ,  G06N3/049 ,  G06N3/082

摘要： A reconfigurable neural network circuit is provided. The reconfigurable neural network circuit comprises an electronic synapse array including multiple synapses interconnecting a plurality of digital electronic neurons. Each neuron comprises an integrator that integrates input spikes and generates a signal when the integrated inputs exceed a threshold. The circuit further comprises a control module for reconfiguring the synapse array. The control module comprises a global final state machine that controls timing for operation of the circuit, and a priority encoder that allows spiking neurons to sequentially access the synapse array.

摘要翻译： 提供可重构神经网络电路。 可重构神经网络电路包括电子突触阵列，其包括互连多个数字电子神经元的多个突触。 每个神经元包括积分器，其对输入尖峰进行积分，并且当集成输入超过阈值时产生信号。 电路还包括用于重新配置突触阵列的控制模块。 控制模块包括控制电路操作的定时的全局最终状态机，以及允许加标神经元依次访问突触阵列的优先编码器。