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    Sub-rate low-swing data receiver
    5.
    发明授权
    Sub-rate low-swing data receiver 有权
    次速低音数据接收机

    公开(公告)号：US09240789B2

    公开(公告)日：2016-01-19

    申请号：US13600534

    申请日：2012-08-31

    申请人： Daniel J. Friedman ,  Yong Liu ,  Jose A. Tierno

    发明人： Daniel J. Friedman ,  Yong Liu ,  Jose A. Tierno

    IPC分类号： H03K19/0175 ,  H03K19/0185

    CPC分类号： H03K19/018521

    摘要： A receiver is adapted to receive an input signal having a first voltage swing and to generate an output signal having a second voltage swing, the output signal being indicative of the input signal, the second voltage swing being greater than the first voltage swing. The receiver includes a first sub-rate receiver block and at least a second sub-rate receiver block. A receiver clock is divided into a first sub-rate clock phase and at least a second sub-rate clock phase, the first sub-rate clock phase being used to drive the first sub-rate receiver block and the second sub-rate clock phase being used to drive the second sub-rate receiver block. Each of the first sub-rate receiver block and the second sub-rate receiver block includes at least one gated-diode sense amplifier.

    摘要翻译： 接收器适于接收具有第一电压摆幅的输入信号并产生具有第二电压摆幅的输出信号，该输出信号表示输入信号，第二电压摆幅大于第一电压摆幅。 接收机包括第一子速率接收器块和至少第二子速率接收器块。 接收机时钟被分为第一子速率时钟相位和至少第二子速率时钟相位，第一子速率时钟相位用于驱动第一子速率接收机模块和第二子速率时钟相位 用于驱动第二子速率接收器块。 第一子速率接收器块和第二子速率接收器块中的每一个包括至少一个门控二极管读出放大器。

    SUB-RATE LOW-SWING DATA RECEIVER
    6.
    发明申请
    SUB-RATE LOW-SWING DATA RECEIVER 有权
    分数低速数据接收器

    公开(公告)号：US20150303920A1

    公开(公告)日：2015-10-22

    申请号：US13600534

    申请日：2012-08-31

    申请人： Daniel J. Friedman ,  Yong Liu ,  Jose A. Tierno

    发明人： Daniel J. Friedman ,  Yong Liu ,  Jose A. Tierno

    IPC分类号： H03K19/0185

    CPC分类号： H03K19/018521

    摘要： A receiver is adapted to receive an input signal having a first voltage swing and to generate an output signal having a second voltage swing, the output signal being indicative of the input signal, the second voltage swing being greater than the first voltage swing. The receiver includes a first sub-rate receiver block and at least a second sub-rate receiver block. A receiver clock is divided into a first sub-rate clock phase and at least a second sub-rate clock phase, the first sub-rate clock phase being used to drive the first sub-rate receiver block and the second sub-rate clock phase being used to drive the second sub-rate receiver block. Each of the first sub-rate receiver block and the second sub-rate receiver block includes at least one gated-diode sense amplifier.

    摘要翻译： 接收器适于接收具有第一电压摆幅的输入信号并产生具有第二电压摆幅的输出信号，该输出信号表示输入信号，第二电压摆幅大于第一电压摆幅。 接收机包括第一子速率接收器块和至少第二子速率接收器块。 接收机时钟被分为第一子速率时钟相位和至少第二子速率时钟相位，第一子速率时钟相位用于驱动第一子速率接收机模块和第二子速率时钟相位 用于驱动第二子速率接收器块。 第一子速率接收器块和第二子速率接收器块中的每一个包括至少一个门控二极管读出放大器。

    PARALLEL PROGRAMMING MULTIPLE PHASE CHANGE MEMORY CELLS
    7.
    发明申请
    PARALLEL PROGRAMMING MULTIPLE PHASE CHANGE MEMORY CELLS 审中-公开
    并行编程多相变化记忆细胞

    公开(公告)号：US20140063925A1

    公开(公告)日：2014-03-06

    申请号：US13434739

    申请日：2012-03-29

    申请人： Daniel J. Friedman ,  Seongwon Kim ,  Yong Liu ,  Bipin Rajendran

    发明人： Daniel J. Friedman ,  Seongwon Kim ,  Yong Liu ,  Bipin Rajendran

    IPC分类号： G11C13/00

    CPC分类号： G11C13/0069 ,  G11C13/0004 ,  G11C2013/0085 ,  G11C2013/0088 ,  G11C2013/0092 ,  G11C2213/79

    摘要： Embodiments of the present invention provide a device comprising a plurality of phase change memory cells, a word line, and a plurality of bit lines. Each phase change memory cell is coupled to a corresponding transistor. Each transistor is coupled to the word line. Each bit line is coupled to a phase change memory cell of the device. The device further comprises a programming circuit configured to program at least one phase change memory cell to the SET state by selectively applying a two-stage waveform to the word line and the bit lines of the device. In a first stage, a first predetermined low voltage and a first predetermined high voltage are applied at the word line and the bit lines, respectively. In a second stage, a second predetermined high voltage and a predetermined voltage with decreasing amplitude are applied at the word line and the bit lines, respectively.

    摘要翻译： 本发明的实施例提供一种包括多个相变存储单元，字线和多个位线的装置。 每个相变存储单元耦合到相应的晶体管。 每个晶体管耦合到字线。 每个位线耦合到器件的相变存储器单元。 该装置还包括编程电路，其被配置为通过选择性地将两级波形应用于该装置的字线和位线来将至少一个相变存储器单元编程到SET状态。 在第一阶段中，分别在字线和位线处施加第一预定低电压和第一预定高电压。 在第二级中，分别在字线和位线处施加具有降低幅度的第二预定高电压和预定电压。

    CALIBRATION SCHEMES FOR CHARGE-RECYCLING STACKED VOLTAGE DOMAINS
    8.
    发明申请
    CALIBRATION SCHEMES FOR CHARGE-RECYCLING STACKED VOLTAGE DOMAINS 有权
    充电回收堆叠电压域的校准方案

    公开(公告)号：US20140176198A1

    公开(公告)日：2014-06-26

    申请号：US13601240

    申请日：2012-08-31

    申请人： Daniel Friedman ,  Yong Liu ,  Jose A. Tierno

    发明人： Daniel Friedman ,  Yong Liu ,  Jose A. Tierno

    IPC分类号： G05F1/46

    CPC分类号： G05F1/56 ,  G05F1/462 ,  H03K5/08 ,  H03K19/0019 ,  H03K19/017509

    摘要： A method and system are disclosed for calibrating a mid-voltage node in an integrated circuit including an input-output circuit having charge-recycling stacked voltage domains including at least first and second voltage domains. In one embodiment, the method comprises transmitting data through the input-output circuit, including transmitting a first portion of the data across the first voltage domain, and transmitting a second portion of the data across the second voltage domain. The method further comprises measuring a specified characteristic of the data transmitted through the input-output circuit; and based on the measured specified characteristic, adjusting a voltage of said mid-voltage node to a defined value. The voltage of the mid-voltage node may be adjusted to accomplish a number of objectives, for example, to achieve a desired trade-off between power and performance, or so that the two voltage domains have the same performance.

    摘要翻译： 公开了一种用于校准集成电路中的中压节点的方法和系统，该集成电路包括具有包括至少第一和第二电压域的电荷再循环层叠电压域的输入 - 输出电路。 在一个实施例中，该方法包括通过输入 - 输出电路传输数据，包括在第一电压域上传输数据的第一部分，以及跨越第二电压域传输数据的第二部分。 该方法还包括测量通过输入 - 输出电路传输的数据的指定特性; 并且基于所测量的特定特性，将所述中间电压节点的电压调整到规定值。 可以调节中间电压节点的电压以实现多个目标，例如，在功率和性能之间实现期望的权衡，或者使得两个电压域具有相同的性能。

    Calibration schemes for charge-recycling stacked voltage domains
    9.
    发明授权
    Calibration schemes for charge-recycling stacked voltage domains 有权
    电荷循环堆叠电压域的校准方案

    公开(公告)号：US08797084B2

    公开(公告)日：2014-08-05

    申请号：US13601240

    申请日：2012-08-31

    申请人： Daniel Friedman ,  Yong Liu ,  Jose A. Tierno

    发明人： Daniel Friedman ,  Yong Liu ,  Jose A. Tierno

    IPC分类号： H03L5/00 ,  H03K5/08

    CPC分类号： G05F1/56 ,  G05F1/462 ,  H03K5/08 ,  H03K19/0019 ,  H03K19/017509

    摘要： A method and system are disclosed for calibrating a mid-voltage node in an integrated circuit including an input-output circuit having charge-recycling stacked voltage domains including at least first and second voltage domains. In one embodiment, the method comprises transmitting data through the input-output circuit, including transmitting a first portion of the data across the first voltage domain, and transmitting a second portion of the data across the second voltage domain. The method further comprises measuring a specified characteristic of the data transmitted through the input-output circuit; and based on the measured specified characteristic, adjusting a voltage of said mid-voltage node to a defined value. The voltage of the mid-voltage node may be adjusted to accomplish a number of objectives, for example, to achieve a desired trade-off between power and performance, or so that the two voltage domains have the same performance.

    摘要翻译： 公开了一种用于校准集成电路中的中压节点的方法和系统，该集成电路包括具有包括至少第一和第二电压域的电荷再循环层叠电压域的输入 - 输出电路。 在一个实施例中，该方法包括通过输入 - 输出电路传输数据，包括在第一电压域上传输数据的第一部分，以及跨越第二电压域传输数据的第二部分。 该方法还包括测量通过输入 - 输出电路传输的数据的指定特性; 并且基于所测量的特定特性，将所述中间电压节点的电压调整到规定值。 可以调节中间电压节点的电压以实现多个目标，例如，在功率和性能之间实现期望的权衡，或者使得两个电压域具有相同的性能。

    Compact low-power asynchronous resistor-based memory read operation and circuit
    10.
    发明授权
    Compact low-power asynchronous resistor-based memory read operation and circuit 有权
    紧凑型低功耗基于异步电阻的存储器读操作和电路

    公开(公告)号：US08824218B2

    公开(公告)日：2014-09-02

    申请号：US13552932

    申请日：2012-07-19

    申请人： Seongwon Kim ,  Yong Liu ,  Bipin Rajendran

    发明人： Seongwon Kim ,  Yong Liu ,  Bipin Rajendran

    IPC分类号： G11C7/06

    CPC分类号： G11C13/004 ,  G11C7/067 ,  G11C11/5678 ,  G11C13/0004

    摘要： A compact, low-power, asynchronous, resistor-based memory read circuit includes a memory cell having a plurality of consecutive memory states, each of said states corresponding to a respective output voltage. A sense amplifier reads the state of the memory cell. The sense amplifier includes a voltage divider configured to receive the output voltage of the memory cell and to output a settled voltage an amplifier having a voltage threshold between the settled voltages associated with two of said consecutive memory states, configured to discriminate between said two consecutive memory states.

    摘要翻译： 紧凑型低功率异步电阻器存储器读取电路包括具有多个连续存储器状态的存储单元，每个所述状态对应于相应的输出电压。 读出放大器读取存储单元的状态。 感测放大器包括分压器，其被配置为接收存储器单元的输出电压并且输出稳定电压，放大器具有在与所述连续存储器状态中的两个相关联的稳定电压之间的电压阈值，其被配置为区分所述两个连续存储器 状态。