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    PHASE CHANGE MEMORY SYNAPTRONIC CIRCUIT FOR SPIKING COMPUTATION, ASSOCIATION AND RECALL
    5.
    发明申请
    PHASE CHANGE MEMORY SYNAPTRONIC CIRCUIT FOR SPIKING COMPUTATION, ASSOCIATION AND RECALL 审中-公开
    相位改变记忆同步电路，用于SPIKING计算，协调和调用

    公开(公告)号：US20120084240A1

    公开(公告)日：2012-04-05

    申请号：US12895710

    申请日：2010-09-30

    申请人： Steven K. Esser ,  Dharmendra S. Modha ,  Anthony Ndirango ,  Bipin Rajendran

    发明人： Steven K. Esser ,  Dharmendra S. Modha ,  Anthony Ndirango ,  Bipin Rajendran

    IPC分类号： G06N3/04

    CPC分类号： G06N3/063

    摘要： Embodiments of the invention are directed to producing spike-timing dependent plasticity using electronic neurons for computation, and pattern matching tasks such as association and recall. In response to an electronic neuron spiking, a spiking signal is sent from the electronic neuron to each axon driver and each dendrite driver connected to the spiking electronic neuron. Each axon driver receiving the spiking signal sends an axonal signal from the axon driver to a variable state resistor. Each dendrite driver receiving the spiking signal sends a dendritic signal from the dendrite driver to the variable state resistor, wherein the variable state resistor couples the axon driver and the dendrite driver. The combination of the axonal and dendritic signals is capable of increasing or decreasing conductance of the variable state resistor.

    摘要翻译： 本发明的实施例涉及使用用于计算的电子神经元和诸如关联和召回的模式匹配任务来产生尖峰时序相关的可塑性。 响应于电子神经元峰值，从电子神经元发送尖峰信号到每个轴突驱动器，并且每个枝晶驱动器连接到尖峰电子神经元。 接收尖峰信号的每个轴突驱动器将轴突信号从轴突驱动器发送到可变状态电阻器。 接收尖峰信号的每个枝晶驱动器将枝晶信号从枝晶驱动器发送到可变状态电阻器，其中可变状态电阻器耦合轴突驱动器和枝晶驱动器。 轴突和树突状信号的组合能够增加或降低可变状态电阻的电导。

    Multi-compartment neurons with neural cores
    6.
    发明授权
    Multi-compartment neurons with neural cores 有权

    公开(公告)号：US09275330B2

    公开(公告)日：2016-03-01

    申请号：US13596278

    申请日：2012-08-28

    申请人： Steven K. Esser ,  Dharmendra S. Modha

    发明人： Steven K. Esser ,  Dharmendra S. Modha

    IPC分类号： G06E1/00 ,  G06N3/063 ,  G06N3/04 ,  G06F9/445

    CPC分类号： G06N3/04 ,  G06F9/44505 ,  G06N3/049 ,  G06N3/063 ,  G06N3/088

    摘要： Embodiments of the invention provide a neural core circuit comprising a synaptic interconnect network including plural electronic synapses for interconnecting one or more source electronic neurons with one or more target electronic neurons. The interconnect network further includes multiple axon paths and multiple dendrite paths. Each synapse is at a cross-point junction of the interconnect network between a dendrite path and an axon path. The core circuit further comprises a routing module maintaining routing information. The routing module routes output from a source electronic neuron to one or more selected axon paths. Each synapse provides a configurable level of signal conduction from an axon path of a source electronic neuron to a dendrite path of a target electronic neuron.

    SCALABLE NEURAL HARDWARE FOR THE NOISY-OR MODEL OF BAYESIAN NETWORKS
    7.
    发明申请
    SCALABLE NEURAL HARDWARE FOR THE NOISY-OR MODEL OF BAYESIAN NETWORKS 有权
    贝叶斯网络噪声或模型的可伸缩神经硬件

    公开(公告)号：US20150286924A1

    公开(公告)日：2015-10-08

    申请号：US13562187

    申请日：2012-07-30

    申请人： John V. Arthur ,  Steven K. Esser ,  Paul A. Merolla ,  Dharmendra S. Modha

    发明人： John V. Arthur ,  Steven K. Esser ,  Paul A. Merolla ,  Dharmendra S. Modha

    IPC分类号： G06N3/08 ,  G06F7/58 ,  G06N7/00 ,  G06N3/04

    CPC分类号： G06N3/08 ,  G06F7/582 ,  G06N3/04 ,  G06N3/0472 ,  G06N3/063 ,  G06N7/005

    摘要： Embodiments of the invention relate to a scalable neural hardware for the noisy-OR model of Bayesian networks. One embodiment comprises a neural core circuit including a pseudo-random number generator for generating random numbers. The neural core circuit further comprises a plurality of incoming electronic axons, a plurality of neural modules, and a plurality of electronic synapses interconnecting the axons to the neural modules. Each synapse interconnects an axon with a neural module. Each neural module receives incoming spikes from interconnected axons. Each neural module represents a noisy-OR gate. Each neural module spikes probabilistically based on at least one random number generated by the pseudo-random number generator unit.

    摘要翻译： 本发明的实施例涉及用于贝叶斯网络的噪声-OR模型的可伸缩神经硬件。 一个实施例包括神经核心电路，其包括用于产生随机数的伪随机数发生器。 神经核心电路还包括多个进入的电子轴突，多个神经模块和将轴突与神经模块相互连接的多个电子突触。 每个突触将轴突与神经模块相互连接。 每个神经模块从相互联系的轴突接收进入的尖峰。 每个神经模块表示噪声或门。 每个神经模块基于由伪随机数发生器单元生成的至少一个随机数来概率地尖峰。

    Multi-processor cortical simulations with reciprocal connections with shared weights
    8.
    发明授权
    Multi-processor cortical simulations with reciprocal connections with shared weights 有权
    多处理器皮质模拟与共享权重的互惠连接

    公开(公告)号：US08924322B2

    公开(公告)日：2014-12-30

    申请号：US13524798

    申请日：2012-06-15

    申请人： Pallab Datta ,  Steven K. Esser ,  Dharmendra S. Modha

    发明人： Pallab Datta ,  Steven K. Esser ,  Dharmendra S. Modha

    IPC分类号： G06N3/00 ,  G06N3/02 ,  G06N3/06

    CPC分类号： G06N3/02 ,  G06N3/049 ,  G06N3/06 ,  G06N3/10

    摘要： Embodiments of the invention relate to distributed simulation frameworks that provide reciprocal communication. One embodiment comprises interconnecting neuron groups on different processors via a plurality of reciprocal communication pathways, and facilitating the exchange of reciprocal spiking communication between two different processors using at least one Ineuron module. Each processor includes at least one neuron group. Each neuron group includes at least one electronic neuron.

    摘要翻译： 本发明的实施例涉及提供相互通信的分布式仿真框架。 一个实施例包括经由多个相互通信路径在不同处理器上互连神经元组，并且促进使用至少一个Ineuron模块交换两个不同处理器之间的相互加速通信。 每个处理器包括至少一个神经元组。 每个神经元组包括至少一个电子神经元。

    CANONICAL SPIKING NEURON NETWORK FOR SPATIOTEMPORAL ASSOCIATIVE MEMORY
    9.
    发明申请
    CANONICAL SPIKING NEURON NETWORK FOR SPATIOTEMPORAL ASSOCIATIVE MEMORY 有权

    公开(公告)号：US20120109863A1

    公开(公告)日：2012-05-03

    申请号：US12828091

    申请日：2010-06-30

    申请人： Steven K. Esser ,  Dharmendra S. Modha ,  Anthony Ndirango

    发明人： Steven K. Esser ,  Dharmendra S. Modha ,  Anthony Ndirango

    IPC分类号： G06N3/063 ,  G06N3/08

    CPC分类号： G06N3/049 ,  G06N3/063 ,  G06N3/08

    摘要： Embodiments of the invention relate to canonical spiking neurons for spatiotemporal associative memory. An aspect of the invention provides a spatiotemporal associative memory including a plurality of electronic neurons having a layered neural net relationship with directional synaptic connectivity. The plurality of electronic neurons configured to detect the presence of a spatiotemporal pattern in a real-time data stream, and extract the spatiotemporal pattern. The plurality of electronic neurons are further configured to, based on learning rules, store the spatiotemporal pattern in the plurality of electronic neurons, and upon being presented with a version of the spatiotemporal pattern, retrieve the stored spatiotemporal pattern.

    Scalable neural hardware for the noisy-OR model of Bayesian networks
    10.
    发明授权
    Scalable neural hardware for the noisy-OR model of Bayesian networks 有权
    贝叶斯网络噪声或模型的可扩展神经硬件

    公开(公告)号：US09189729B2

    公开(公告)日：2015-11-17

    申请号：US13562187

    申请日：2012-07-30

    申请人： John V. Arthur ,  Steven K. Esser ,  Paul A. Merolla ,  Dharmendra S. Modha

    发明人： John V. Arthur ,  Steven K. Esser ,  Paul A. Merolla ,  Dharmendra S. Modha

    IPC分类号： G06N3/04 ,  G06N3/08 ,  G06F7/58 ,  G06N7/00

    CPC分类号： G06N3/08 ,  G06F7/582 ,  G06N3/04 ,  G06N3/0472 ,  G06N3/063 ,  G06N7/005

    摘要： Embodiments of the invention relate to a scalable neural hardware for the noisy-OR model of Bayesian networks. One embodiment comprises a neural core circuit including a pseudo-random number generator for generating random numbers. The neural core circuit further comprises a plurality of incoming electronic axons, a plurality of neural modules, and a plurality of electronic synapses interconnecting the axons to the neural modules. Each synapse interconnects an axon with a neural module. Each neural module receives incoming spikes from interconnected axons. Each neural module represents a noisy-OR gate. Each neural module spikes probabilistically based on at least one random number generated by the pseudo-random number generator unit.

    摘要翻译： 本发明的实施例涉及用于贝叶斯网络的噪声-OR模型的可伸缩神经硬件。 一个实施例包括神经核心电路，其包括用于产生随机数的伪随机数发生器。 神经核心电路还包括多个输入电子轴突，多个神经模块以及将轴突与神经模块互连的多个电子突触。 每个突触将轴突与神经模块相互连接。 每个神经模块从相互联系的轴突接收进入的尖峰。 每个神经模块表示噪声或门。 每个神经模块基于由伪随机数发生器单元生成的至少一个随机数来概率地尖峰。