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    Fluorescence emission ratio imaging thermography for use in heat transfer analysis
    2.
    发明授权
    Fluorescence emission ratio imaging thermography for use in heat transfer analysis 失效
    用于传热分析的荧光发射比成像热成像

    公开(公告)号：US06648506B2

    公开(公告)日：2003-11-18

    申请号：US09949281

    申请日：2001-09-07

    申请人： John J. McGrath ,  Bin Lian

    发明人： John J. McGrath ,  Bin Lian

    IPC分类号： G01K1100

    CPC分类号： G01K11/20 ,  G01K11/3213

    摘要： The present invention provides a fluorescent imaging thermographic method and system for use particularly in surface temperature measurements, which are reproducible over time. The invention provides a temperature-sensitive fluorescent probe comprising a rare earth compound in an ultraviolet and fluorescence transparent medium wherein the intensity of fluorescence varies as the temperature varies, in particular, provided are probes comprising Europium(1,1,1,5,5,5-hexafluoroacetylacetone)3 for measuring temperatures greater than 24° C., and Terbium(1,1,1,5,5,5-hexafluoroacetylacetone)3 for measuring temperatures less than 24° C. The probe is applied as a layer to a surface, exposed to fluorescence-inducing energy, and emitted fluorescence measured. A ratio imaging algorithm enables the temperature at each location on the surface to be determined.

    摘要翻译： 本发明提供了一种特别用于表面温度测量的荧光成像热成像方法和系统，其随时间可重现。 本发明提供了一种在紫外和荧光透明介质中包含稀土化合物的温度敏感荧光探针，其中荧光强度随温度变化而变化，特别是提供的是包含铕（1,1,1,5,5 ，5-六氟乙酰丙酮）3，测定温度大于24℃的铽（1,1,1,5,5,5-六氟乙酰丙酮）3。测定温度低于24℃的探针作为层 到表面，暴露于荧光诱导能量，并发射荧光测量。 比例成像算法可以确定表面上每个位置的温度。

    Vapor chamber active heat sink
    3.
    发明授权
    Vapor chamber active heat sink 有权
    蒸气室主动散热器

    公开(公告)号：US06550531B1

    公开(公告)日：2003-04-22

    申请号：US09572926

    申请日：2000-05-16

    申请人： Damion T. Searls ,  Terrance J. Dishongh ,  Prateek J. Dujari ,  Bin Lian

    发明人： Damion T. Searls ,  Terrance J. Dishongh ,  Prateek J. Dujari ,  Bin Lian

    IPC分类号： F28D1500

    CPC分类号： F28D15/0233 ,  F28D2021/0029 ,  F28F3/022 ,  F28F3/04 ,  H01L23/427 ,  H01L2224/16 ,  H01L2224/73253

    摘要： A heat dissipation device including a base portion having a plurality of projections extending therefrom. The base portion may have a vapor chamber defined therein and may have first surface sloped from a central apex portion to edges of the base portion. The vapor chamber includes at least one extension on a vapor chamber upper surface which is adapted to direct a condensed working fluid toward a desired location on a vapor chamber lower surface. The vapor chamber lower surface may have at least one depression to collect a greater portion of the working fluid in a desired location(s).

    摘要翻译： 一种散热装置，包括具有从其延伸的多个突起的基部。 基部可以具有限定在其中的蒸气室，并且可以具有从中心顶点部分到基部的边缘的第一表面倾斜。 蒸气室包括在蒸气室上表面上的至少一个延伸部，其适于将冷凝的工作流体引导到蒸气室下表面上的期望位置。 蒸汽室下表面可以具有至少一个凹陷以在期望的位置收集更大部分的工作流体。

    Process for local on-chip cooling of semiconductor devices using buried microchannels
    6.
    发明授权
    Process for local on-chip cooling of semiconductor devices using buried microchannels 失效
    使用埋入微通道的半导体器件局部片上冷却的工艺

    公开(公告)号：US06521516B2

    公开(公告)日：2003-02-18

    申请号：US09895136

    申请日：2001-06-29

    申请人： Franklin G. Monzon ,  Prateek Dujari ,  Bin Lian

    发明人： Franklin G. Monzon ,  Prateek Dujari ,  Bin Lian

    IPC分类号： H01L21425

    CPC分类号： H01L23/473 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

    摘要： A method and apparatus comprising using buried microchannels to cool specific areas of a substrate over which high heat generating elements of integrated circuits, circuits or devices are processed is disclosed. In one embodiment of the method and apparatus comprise running a cooling fluid thorough a buried microchannel under a heat generating element to locally cool the substrate.

    摘要翻译： 公开了一种方法和装置，其包括使用掩埋微通道来冷却集成电路，电路或器件的高发热元件被处理的衬底的特定区域。 在该方法和设备的一个实施例中，包括通过发热元件下面的埋入微通道运行冷却流体以局部冷却基板。

    Circuit card assembly having controlled vibrational properties
    7.
    发明授权
    Circuit card assembly having controlled vibrational properties 失效
    电路卡组件具有受控的振动特性

    公开(公告)号：US06486589B1

    公开(公告)日：2002-11-26

    申请号：US09563378

    申请日：2000-05-03

    申请人： Prateek Dujari ,  Terrance J. Dishongh ,  Bin Lian ,  Damion T. Searls

    发明人： Prateek Dujari ,  Terrance J. Dishongh ,  Bin Lian ,  Damion T. Searls

    IPC分类号： B06B106

    CPC分类号： H05K1/0271 ,  F16F15/005 ,  H05K1/181 ,  H05K2201/10083 ,  H05K2201/10151 ,  H05K2201/2045

    摘要： Piezoelectric wafers are affixed to a circuit card to control displacement of the circuit card when vibrated. A trigger wafer located at an anti-node of the dominant mode shape produces a voltage as a function of modal displacement. A control system responsive to the trigger wafer produces voltages that are applied to flex wafers at a different anti-node of the dominant mode shape. The flex wafers expand and contract in a manner that reduces the modal displacement of the circuit card. Multiple flex wafers can exist, affixed to the circuit card substantially opposite each other, or a single flex wafer can exist with a single trigger wafer. The trigger wafer can be located substantially opposite the flex wafer or can be located elsewhere on the circuit card.

    摘要翻译： 压电晶片固定在电路卡上，以控制振动时电路卡的位移。 位于主模式的反节点处的触发晶片产生作为模态位移的函数的电压。 响应于触发晶片的控制系统产生施加到主模式形状的不同反节点处的柔性晶片的电压。 柔性晶片以减小电路卡的模态位移的方式膨胀和收缩。 可以存在多个柔性晶片，其固定到基本上彼此相对的电路卡，或者单个触发晶片可以存在单个柔性晶片。 触发晶片可以位于基本上与柔性晶片相对的位置，或者可以位于电路卡上的其他位置。

    Surface mount connector lead
    10.
    发明授权
    Surface mount connector lead 失效
    表面贴装连接器引线

    公开(公告)号：US06774310B1

    公开(公告)日：2004-08-10

    申请号：US09698898

    申请日：2000-10-27

    申请人： Terrance J. Dishongh ,  Prateek J. Dujari ,  Bin Lian ,  Damion T. Searls

    发明人： Terrance J. Dishongh ,  Prateek J. Dujari ,  Bin Lian ,  Damion T. Searls

    IPC分类号： H01R402

    CPC分类号： H01R12/57 ,  H01R12/7011 ,  H01R12/707 ,  H05K3/3426 ,  Y02P70/613

    摘要： An enhanced joint thickness lead used for surface mounting electronic devices to a substrate, wherein a portion of the enhanced joint thickness lead that is substantially parallel to the substance. The enhanced joint thickness lead includes an arcuate structure, which provides an enhanced joint thickness for the solder used to connect the lead to the substrate. The enhanced joint thickness of the solder results in a more robust attachment of the electronic device.

    摘要翻译： 用于将电子器件表面安装到基底的增强的接合厚度引线，其中增强的接合厚度引线的一部分基本上平行于物质。 增强的接头厚度引线包括弓形结构，其为用于将引线连接到衬底的焊料提供增强的接合厚度。 焊料的增强的接合厚度导致电子器件的更牢固的附着。