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    Dual issuing of complex instruction set instructions
    2.
    发明授权
    Dual issuing of complex instruction set instructions 有权
    双重发出复杂的指令集指令

    公开(公告)号：US09104399B2

    公开(公告)日：2015-08-11

    申请号：US12645716

    申请日：2009-12-23

    申请人： Fadi Busaba ,  Brian Curran ,  Lee Eisen ,  Christian Jacobi ,  David A. Schroter ,  Eric Schwarz

    发明人： Fadi Busaba ,  Brian Curran ,  Lee Eisen ,  Christian Jacobi ,  David A. Schroter ,  Eric Schwarz

    IPC分类号： G06F15/00 ,  G06F9/30 ,  G06F9/40 ,  G06F9/38

    CPC分类号： G06F9/3001 ,  G06F9/30043 ,  G06F9/3017 ,  G06F9/3836 ,  G06F9/3867

    摘要： A system and method for issuing a processor instruction to multiple processing sections arranged in an out-of-order processing pipeline architecture. The multiple processing sections include a first execution unit with a pipeline length and a second execution unit operating upon data produced by the first execution unit. An instruction issue unit accepts a complex instruction that is cracked into respective micro-ops for the first execution unit and the second execution unit. The instruction issue unit issues the first micro-op to the first execution unit to produce intermediate data. The instruction issue unit then delays for a time period corresponding to the processing pipeline length of the first execution unit. After the delay, a second micro-op is issued to the second execution unit.

    摘要翻译： 一种用于向处理流水线结构排列的多个处理部分发出处理器指令的系统和方法。 多个处理部分包括具有流水线长度的第一执行单元和对由第一执行单元产生的数据进行操作的第二执行单元。 指令发布单元接受对于第一执行单元和第二执行单元破解为相应微操作的复杂指令。 指令发布单元向第一执行单元发出第一微操作以产生中间数据。 然后，指令发布单元延迟与第一执行单元的处理流水线长度对应的时间段。 在延迟之后，向第二执行单元发出第二个微操作。

    Custom event and attribute generation for use in website traffic data collection
    5.
    发明授权
    Custom event and attribute generation for use in website traffic data collection 有权

    公开(公告)号：US10205623B2

    公开(公告)日：2019-02-12

    申请号：US10608442

    申请日：2003-06-26

    申请人： Brett Error ,  Chris Error ,  Brian Curran

    发明人： Brett Error ,  Chris Error ,  Brian Curran

    IPC分类号： H04L29/06 ,  H04L29/08

    摘要： A method and system for the efficient customization of website tracking data includes a data collector with a user interface for assigning custom events and attributes to events occurring on a website. The data collector receives custom tracking data from the website in response to the occurrence of an event to be tracked. Customization of tracking data is achieved through the use of an embedded tracking code and associated data collection file. The embedded tracking code is configured to report tracking data customized for the website. The data collection server is configured via a graphical user interface to receive and store the customized tracking data. A configuration string from the data collector is inserted into the data collection file on the web site. In this manner, the data collection server and website is customized to collect customized tracking data efficiently without assistance from others.

    Cracking destructively overlapping operands in variable length instructions
    6.
    发明授权
    Cracking destructively overlapping operands in variable length instructions 有权
    以可变长度指令破坏性地重叠操作数

    公开(公告)号：US08645669B2

    公开(公告)日：2014-02-04

    申请号：US12774299

    申请日：2010-05-05

    申请人： Khary J. Alexander ,  Fadi Busaba ,  Brian Curran ,  Bruce Giamei ,  Christian Jacobi

    发明人： Khary J. Alexander ,  Fadi Busaba ,  Brian Curran ,  Bruce Giamei ,  Christian Jacobi

    IPC分类号： G06F9/30

    CPC分类号： G06F9/30145 ,  G06F9/30032 ,  G06F9/30043 ,  G06F9/30149 ,  G06F9/3016

    摘要： A method, information processing system, and computer program product manage computer executable instructions. At least one machine instruction for execution is received. The at least one machine instruction is analyzed. The machine instruction is identified as a predefined instruction for storing a variable length first operand in a memory location. Responsive to this identification and based on fields of the machine instruction, a relative location of a variable length second operand of the instruction with location of the first operand is determined. Responsive to the relative location having the predefined relationship, a first cracking operation is performed. The first cracking operation cracks the instruction into a first set of micro-ops (Uops) to be executed in parallel. The first set of Uops is for storing a first plurality of first blocks in the first operand. Each of said first block to be stored are identical. The first set Uops are executed.

    摘要翻译： 一种方法，信息处理系统和计算机程序产品管理计算机可执行指令。 接收至少一个用于执行的机器指令。 分析至少一个机器指令。 机器指令被识别为用于将可变长度的第一操作数存储在存储器位置中的预定义指令。 响应于该识别并且基于机器指令的字段，确定指令的可变长度第二操作数与第一操作数的位置的相对位置。 响应于具有预定关系的相对位置，执行第一裂解操作。 第一个破解操作将指令分解为并行执行的第一组微操作（Uop）。 第一组Uops用于在第一操作数中存储第一多个第一块。 要存储的所述第一块的每个都是相同的。 第一组Uops被执行。

    CRACKING DESTRUCTIVELY OVERLAPPING OPERANDS IN VARIABLE LENGTH INSTRUCTIONS
    7.
    发明申请
    CRACKING DESTRUCTIVELY OVERLAPPING OPERANDS IN VARIABLE LENGTH INSTRUCTIONS 有权
    在可变长度指令中打破破坏性重复操作

    公开(公告)号：US20110276764A1

    公开(公告)日：2011-11-10

    申请号：US12774299

    申请日：2010-05-05

    申请人： Khary J. Alexander ,  Fadi Busaba ,  Brian Curran ,  Bruce Giamei ,  Christian Jacobi

    发明人： Khary J. Alexander ,  Fadi Busaba ,  Brian Curran ,  Bruce Giamei ,  Christian Jacobi

    IPC分类号： G06F9/30 ,  G06F12/08 ,  G06F9/312

    CPC分类号： G06F9/30145 ,  G06F9/30032 ,  G06F9/30043 ,  G06F9/30149 ,  G06F9/3016

    摘要： A method, information processing system, and computer program product manage computer executable instructions. At least one machine instruction for execution is received. The at least one machine instruction is analyzed. The machine instruction is identified as a predefined instruction for storing a variable length first operand in a memory location. Responsive to this identification and based on fields of the machine instruction, a relative location of a variable length second operand of the instruction with location of the first operand is determined. Responsive to the relative location having the predefined relationship, a first cracking operation is performed. The first cracking operation cracks the instruction into a first set of micro-ops (Uops) to be executed in parallel. The second set of Uops is for storing a first plurality of first blocks in the first operand. Each of said first block to be stored are identical. The first set Uops are executed.

    摘要翻译： 一种方法，信息处理系统和计算机程序产品管理计算机可执行指令。 接收至少一个用于执行的机器指令。 分析至少一个机器指令。 机器指令被识别为用于将可变长度的第一操作数存储在存储器位置中的预定义指令。 响应于该识别并且基于机器指令的字段，确定指令的可变长度第二操作数与第一操作数的位置的相对位置。 响应于具有预定关系的相对位置，执行第一裂解操作。 第一个破解操作将指令分解为并行执行的第一组微操作（Uop）。 第二组Uop用于在第一操作数中存储第一多个第一块。 要存储的所述第一块的每个都是相同的。 第一组Uops被执行。

    INSTRUCTION CRACKING AND ISSUE SHORTENING BASED ON INSTRUCTION BASE FIELDS, INDEX FIELDS, OPERAND FIELDS, AND VARIOUS OTHER INSTRUCTION TEXT BITS
    8.
    发明申请
    INSTRUCTION CRACKING AND ISSUE SHORTENING BASED ON INSTRUCTION BASE FIELDS, INDEX FIELDS, OPERAND FIELDS, AND VARIOUS OTHER INSTRUCTION TEXT BITS 有权
    基于指示基地字段，索引字段，操作字段以及各种其他指令文本位置的指令性破解和问题解决

    公开(公告)号：US20110252220A1

    公开(公告)日：2011-10-13

    申请号：US12757330

    申请日：2010-04-09

    申请人： Fadi BUSABA ,  Brian CURRAN ,  Lee EISEN ,  Bruce GIAMEI ,  David HUTTON

    发明人： Fadi BUSABA ,  Brian CURRAN ,  Lee EISEN ,  Bruce GIAMEI ,  David HUTTON

    IPC分类号： G06F9/44 ,  G06F9/30

    CPC分类号： G06F9/3017 ,  G06F9/30032 ,  G06F9/30054 ,  G06F9/30058

    摘要： A method, information processing system, and computer program product crack and/or shorten computer executable instructions. At least one instruction is received. The at least on instruction is analyzed. An instruction type associated with the at least one instruction is identified. At least one of a base field, an index field, one or more operands, and a mask field of the instruction are analyzed. At least one of the following is then performed: the at least one instruction is organized into a set of unit of operation; and the at least one instruction is shortened. The set of unit of operations is then executed.

    摘要翻译： 一种方法，信息处理系统和计算机程序产品破解和/或缩短计算机可执行指令。 至少接收一条指令。 至少对指令进行分析。 识别与该至少一条指令相关联的指令类型。 分析指令的基本字段，索引字段，一个或多个操作数和掩码字段中的至少一个。 然后执行以下中的至少一个：将至少一个指令组织成一组操作单元; 并且至少一个指令被缩短。 然后执行一组操作单元。

    Inverting data on result bus to prepare for instruction in the next cycle for high frequency execution units
    9.
    发明申请
    Inverting data on result bus to prepare for instruction in the next cycle for high frequency execution units 失效

    公开(公告)号：US20060184773A1

    公开(公告)日：2006-08-17

    申请号：US11056894

    申请日：2005-02-11

    申请人： Brian Curran ,  Ashutosh Goyal ,  Michael Vaden ,  David Webber

    发明人： Brian Curran ,  Ashutosh Goyal ,  Michael Vaden ,  David Webber

    IPC分类号： G06F9/44

    CPC分类号： G06F9/3001 ,  G06F9/3867

    摘要： A method of operating an arithmetic logic unit (ALU) by inverting a result of an operation to be executed during a current cycle in response to control signals from instruction decode logic which indicate that a later operation will require a complement of the result, wherein the result is inverted during the current cycle. The later operation may be a subtraction operation that immediately follows the first operation. The later instruction is decoded prior to the current cycle to control the inversion in the ALU. The ALU includes an adder, a rotator, and a data manipulation unit which invert the result during the current cycle in response to an invert control signal. The second operation subtracts the result during a subsequent cycle in which a carry control signal to the adder is enabled, and the rotator and the data manipulation unit are disabled. The ALU may be used in an execution unit of a microprocessor, such as a fixed-point unit.