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    Cracking destructively overlapping operands in variable length instructions
    2.
    发明授权
    Cracking destructively overlapping operands in variable length instructions 有权
    以可变长度指令破坏性地重叠操作数

    公开(公告)号：US08645669B2

    公开(公告)日：2014-02-04

    申请号：US12774299

    申请日：2010-05-05

    申请人： Khary J. Alexander ,  Fadi Busaba ,  Brian Curran ,  Bruce Giamei ,  Christian Jacobi

    发明人： Khary J. Alexander ,  Fadi Busaba ,  Brian Curran ,  Bruce Giamei ,  Christian Jacobi

    IPC分类号： G06F9/30

    CPC分类号： G06F9/30145 ,  G06F9/30032 ,  G06F9/30043 ,  G06F9/30149 ,  G06F9/3016

    摘要： A method, information processing system, and computer program product manage computer executable instructions. At least one machine instruction for execution is received. The at least one machine instruction is analyzed. The machine instruction is identified as a predefined instruction for storing a variable length first operand in a memory location. Responsive to this identification and based on fields of the machine instruction, a relative location of a variable length second operand of the instruction with location of the first operand is determined. Responsive to the relative location having the predefined relationship, a first cracking operation is performed. The first cracking operation cracks the instruction into a first set of micro-ops (Uops) to be executed in parallel. The first set of Uops is for storing a first plurality of first blocks in the first operand. Each of said first block to be stored are identical. The first set Uops are executed.

    摘要翻译： 一种方法，信息处理系统和计算机程序产品管理计算机可执行指令。 接收至少一个用于执行的机器指令。 分析至少一个机器指令。 机器指令被识别为用于将可变长度的第一操作数存储在存储器位置中的预定义指令。 响应于该识别并且基于机器指令的字段，确定指令的可变长度第二操作数与第一操作数的位置的相对位置。 响应于具有预定关系的相对位置，执行第一裂解操作。 第一个破解操作将指令分解为并行执行的第一组微操作（Uop）。 第一组Uops用于在第一操作数中存储第一多个第一块。 要存储的所述第一块的每个都是相同的。 第一组Uops被执行。

    CRACKING DESTRUCTIVELY OVERLAPPING OPERANDS IN VARIABLE LENGTH INSTRUCTIONS
    3.
    发明申请
    CRACKING DESTRUCTIVELY OVERLAPPING OPERANDS IN VARIABLE LENGTH INSTRUCTIONS 有权
    在可变长度指令中打破破坏性重复操作

    公开(公告)号：US20110276764A1

    公开(公告)日：2011-11-10

    申请号：US12774299

    申请日：2010-05-05

    申请人： Khary J. Alexander ,  Fadi Busaba ,  Brian Curran ,  Bruce Giamei ,  Christian Jacobi

    发明人： Khary J. Alexander ,  Fadi Busaba ,  Brian Curran ,  Bruce Giamei ,  Christian Jacobi

    IPC分类号： G06F9/30 ,  G06F12/08 ,  G06F9/312

    CPC分类号： G06F9/30145 ,  G06F9/30032 ,  G06F9/30043 ,  G06F9/30149 ,  G06F9/3016

    摘要： A method, information processing system, and computer program product manage computer executable instructions. At least one machine instruction for execution is received. The at least one machine instruction is analyzed. The machine instruction is identified as a predefined instruction for storing a variable length first operand in a memory location. Responsive to this identification and based on fields of the machine instruction, a relative location of a variable length second operand of the instruction with location of the first operand is determined. Responsive to the relative location having the predefined relationship, a first cracking operation is performed. The first cracking operation cracks the instruction into a first set of micro-ops (Uops) to be executed in parallel. The second set of Uops is for storing a first plurality of first blocks in the first operand. Each of said first block to be stored are identical. The first set Uops are executed.

    摘要翻译： 一种方法，信息处理系统和计算机程序产品管理计算机可执行指令。 接收至少一个用于执行的机器指令。 分析至少一个机器指令。 机器指令被识别为用于将可变长度的第一操作数存储在存储器位置中的预定义指令。 响应于该识别并且基于机器指令的字段，确定指令的可变长度第二操作数与第一操作数的位置的相对位置。 响应于具有预定关系的相对位置，执行第一裂解操作。 第一个破解操作将指令分解为并行执行的第一组微操作（Uop）。 第二组Uop用于在第一操作数中存储第一多个第一块。 要存储的所述第一块的每个都是相同的。 第一组Uops被执行。

    Determining the logical address of a transaction abort
    8.
    发明授权
    Determining the logical address of a transaction abort 有权
    确定事务中止的逻辑地址

    公开(公告)号：US09223687B2

    公开(公告)日：2015-12-29

    申请号：US13524342

    申请日：2012-06-15

    申请人： Khary J. Alexander ,  Jonathan T. Hsieh ,  Christian Jacobi

    发明人： Khary J. Alexander ,  Jonathan T. Hsieh ,  Christian Jacobi

    IPC分类号： G06F12/02 ,  G06F12/00 ,  G06F12/08 ,  G06F9/30 ,  G06F9/38

    CPC分类号： G06F12/00 ,  G06F9/3004 ,  G06F9/30087 ,  G06F9/3834 ,  G06F9/3859 ,  G06F12/08 ,  G06F12/0808 ,  G06F12/0815 ,  G06F12/0822 ,  G06F12/0831 ,  G06F12/0833 ,  G06F12/0891

    摘要： Embodiments relate to determining the logical address of a transaction abort. In an embodiment, one or more instructions are received are received from an application. The one or more instructions are executed within a first transaction. The first transaction delays committing stores to memory until it has completed. At least one of the one or more instructions includes a first logical memory address. The first logical memory address corresponds to a first memory address in a memory system. It is determined if the first memory address is equal to a second memory address that is stored in a conflict register. Based on determining that they are equal the first logical memory address is saved as a logical address associated with a cross invalidate (XI) signal at a location available to the application.

    摘要翻译： 实施例涉及确定事务中止的逻辑地址。 在一个实施例中，从应用程序接收一个或多个接收的指令。 一个或多个指令在第一事务中执行。 第一个交易延迟将存储提交到内存，直到它完成。 所述一个或多个指令中的至少一个包括第一逻辑存储器地址。 第一逻辑存储器地址对应于存储器系统中的第一存储器地址。 确定第一存储器地址是否等于存储在冲突寄存器中的第二存储器地址。 基于确定它们相等，第一逻辑存储器地址被保存为与应用可用的位置处的交叉无效（XI）信号相关联的逻辑地址。