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    Manufacturable recessed strained RSD structure and process for advanced CMOS
    1.
    发明授权
    Manufacturable recessed strained RSD structure and process for advanced CMOS 失效
    可制造的凹陷应变RSD结构和高级CMOS工艺

    公开(公告)号：US07446005B2

    公开(公告)日：2008-11-04

    申请号：US11433266

    申请日：2006-05-12

    申请人： Brian Messenger ,  Renee T. Mo ,  Dominic J. Schepis

    发明人： Brian Messenger ,  Renee T. Mo ,  Dominic J. Schepis

    IPC分类号： H01L21/336

    CPC分类号： H01L29/66742 ,  H01L29/7842 ,  H01L29/78687

    摘要： A manufacturable way to recess silicon that employs an end point detection method for the recess etch and allows tight tolerances on the recess is described for fabricating a strained raised source/drain layer. The method includes forming a monolayer oxygen and carbon on a surface of a doped semiconductor substrate; forming an epi Si layer atop the doped semiconductor substrate; forming at least one gate region on the epi Si layer; selectively etching exposed portions of the epi layer, not protected by the gate region, stopping on and exposing the doped semiconductor substrate using end point detection; and forming a strained SiGe layer on the exposed doped semiconductor substrate. The strained SiGe layer severs as a raised layer in which source/drain diffusion regions can be subsequently formed.

    摘要翻译： 为了制造应变升高的源极/漏极层，描述了用于凹陷蚀刻采用端点检测方法以及允许在凹槽上的紧密公差的硅的可制造方法。 该方法包括在掺杂半导体衬底的表面上形成单层氧和碳; 在掺杂半导体衬底的顶部形成外延Si层; 在外延Si层上形成至少一个栅极区; 选择性地蚀刻未被栅极区域保护的外延层的暴露部分，使用端点检测停止并暴露掺杂半导体衬底; 以及在所述暴露的掺杂半导体衬底上形成应变SiGe层。 应变SiGe层作为凸起层切断，其中可以随后形成源/漏扩散区。

    Semiconductor device having a strained raised source/drain
    2.
    发明授权
    Semiconductor device having a strained raised source/drain 失效
    具有应变升高源极/漏极的半导体器件

    公开(公告)号：US07115955B2

    公开(公告)日：2006-10-03

    申请号：US10710738

    申请日：2004-07-30

    申请人： Brian Messenger ,  Renee T. Mo ,  Dominic J. Schepis

    发明人： Brian Messenger ,  Renee T. Mo ,  Dominic J. Schepis

    IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

    CPC分类号： H01L29/66742 ,  H01L29/7842 ,  H01L29/78687

    摘要： A manufacturable way to recess silicon that employs an end point detection method for the recess etch and allows tight tolerances on the recess is described for fabricating a strained raised source/drain layer. The method includes forming a monolayer comprising oxygen and carbon on a surface of a doped semiconductor substrate; forming an epi Si layer atop the doped semiconductor substrate; forming at least one gate region on the epi Si layer; selectively etching exposed portions of the epi layer, not protected by the gate region, stopping on and exposing the doped semiconductor substrate using end point detection; and forming a strained SiGe layer on the exposed doped semiconductor substrate. The strained SiGe layer serves as a raised layer in which source/drain diffusion regions can be subsequently formed.

    摘要翻译： 为了制造应变升高的源极/漏极层，描述了用于凹陷蚀刻采用端点检测方法以及允许在凹槽上的紧密公差的硅的可制造方法。 该方法包括在掺杂的半导体衬底的表面上形成包含氧和碳的单层; 在掺杂半导体衬底的顶部形成外延Si层; 在外延Si层上形成至少一个栅极区; 选择性地蚀刻未被栅极区域保护的外延层的暴露部分，使用端点检测停止并暴露掺杂半导体衬底; 以及在所述暴露的掺杂半导体衬底上形成应变SiGe层。 应变SiGe层用作可以随后形成源/漏扩散区的凸起层。

    Method of fabricating isolated capacitors and structure thereof
    4.
    发明授权
    Method of fabricating isolated capacitors and structure thereof 有权
    隔离电容器的制造方法及其结构

    公开(公告)号：US08652925B2

    公开(公告)日：2014-02-18

    申请号：US12838515

    申请日：2010-07-19

    申请人： Oh-Jung Kwon ,  Junedong Lee ,  Paul C. Parries ,  Dominic J. Schepis

    发明人： Oh-Jung Kwon ,  Junedong Lee ,  Paul C. Parries ,  Dominic J. Schepis

    IPC分类号： H01L21/20

    CPC分类号： H01L21/2007 ,  G06F17/5068 ,  H01L21/76224 ,  H01L21/7624 ,  H01L21/76251 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/0207 ,  H01L27/10829 ,  H01L27/10861 ,  H01L27/1087 ,  H01L27/1203 ,  H01L28/40 ,  H01L28/90 ,  H01L29/66181

    摘要： A structure and method is provided for fabricating isolated capacitors. The method includes simultaneously forming a plurality of deep trenches and one or more isolation trenches surrounding a group or array of the plurality of deep trenches through a SOI and doped poly layer, to an underlying insulator layer. The method further includes lining the plurality of deep trenches and one or more isolation trenches with an insulator material. The method further includes filling the plurality of deep trenches and one or more isolation trenches with a conductive material on the insulator material. The deep trenches form deep trench capacitors and the one or more isolation trenches form one or more isolation plates that isolate at least one group or array of the deep trench capacitors from another group or array of the deep trench capacitors.

    摘要翻译： 提供了用于制造隔离电容器的结构和方法。 该方法包括同时形成多个深沟槽和围绕多个深沟槽的一组或多个阵列的一个或多个隔离沟槽，其通过SOI和掺杂多晶硅层形成到下面的绝缘体层。 该方法还包括用绝缘体材料衬套多个深沟槽和一个或多个隔离沟槽。 该方法还包括在绝缘体材料上用导电材料填充多个深沟槽和一个或多个隔离沟槽。 深沟槽形成深沟槽电容器，并且一个或多个隔离沟槽形成一个或多个隔离板，其将深沟槽电容器的至少一组或阵列与另一组或深沟槽电容器阵列隔离开来。

    SILICON GERMANIUM FILM FORMATION METHOD AND STRUCTURE
    5.
    发明申请
    SILICON GERMANIUM FILM FORMATION METHOD AND STRUCTURE 有权
    硅锗膜形成方法和结构

    公开(公告)号：US20120205749A1

    公开(公告)日：2012-08-16

    申请号：US13025474

    申请日：2011-02-11

    申请人： Ashima B. Chakravarti ,  Abhishek Dube ,  Dominic J. Schepis

    发明人： Ashima B. Chakravarti ,  Abhishek Dube ,  Dominic J. Schepis

    IPC分类号： H01L27/092 ,  H01L21/762 ,  H01L21/8238

    CPC分类号： H01L21/823814 ,  H01L21/76224 ,  H01L21/823807

    摘要： Epitaxial deposition of silicon germanium in a semiconductor device is achieved without using masks. Nucleation delays induced by interactions with dopants present before deposition of the silicon germanium are used to determine a period over which an exposed substrate surface may be subjected to epitaxial deposition to form a layer of SiGe on desired parts with substantially no deposition on other parts. Dopant concentration may be changed to achieve desired thicknesses within preferred deposition times. Resulting deposited SiGe is substantially devoid of growth edge effects.

    摘要翻译： 在不使用掩模的情况下实现硅锗在半导体器件中的外延沉积。 使用在沉积硅锗之前与存在的掺杂剂的相互作用引起的成核延迟来确定暴露的衬底表面可以经历外延沉积以在所需部分上形成SiGe层的周期，而在其它部分上基本上没有沉积。 可以改变掺杂剂浓度以在优选的沉积时间内实现期望的厚度。 导致沉积的SiGe基本上没有生长边缘效应。

    Pre-epitaxial disposable spacer integration scheme with very low temperature selective epitaxy for enhanced device performance
    9.
    发明授权
    Pre-epitaxial disposable spacer integration scheme with very low temperature selective epitaxy for enhanced device performance 有权
    具有非常低温选择性外延的预外延一次性间隔物集成方案，以提高器件性能

    公开(公告)号：US07682915B2

    公开(公告)日：2010-03-23

    申请号：US12100644

    申请日：2008-04-10

    申请人： Huajie Chen ,  Judson R. Holt ,  Kern Rim ,  Dominic J. Schepis

    发明人： Huajie Chen ,  Judson R. Holt ,  Kern Rim ,  Dominic J. Schepis

    IPC分类号： H01L21/336

    CPC分类号： H01L21/823864 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823468 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

    摘要： The embodiments of the invention provide a method, etc. for a pre-epitaxial disposable spacer integration scheme with very low temperature selective epitaxy for enhanced device performance. More specifically, one method begins by forming a first gate and a second gate on a substrate. Next, an oxide layer is formed on the first and second gates; and, a nitride layer is formed on the oxide layer. Portions of the nitride layer proximate the first gate, portions of the oxide layer proximate the first gate, and portions of the substrate proximate the first gate are removed so as to form source and drain recesses proximate the first gate. Following this, the method removes remaining portions of the nitride layer, including exposing remaining portions of the oxide layer. The removal of the remaining portions of the nitride layer only exposes the remaining portions of the oxide layer and the source and drain recesses.

    摘要翻译： 本发明的实施例提供了一种用于具有非常低的温度选择性外延的预外延一次性间隔物集成方案的方法等，以增强器件性能。 更具体地，一种方法是通过在衬底上形成第一栅极和第二栅极开始的。 接下来，在第一和第二栅极上形成氧化物层; 并且在氧化物层上形成氮化物层。 接近第一栅极的氮化物层的部分，靠近第一栅极的氧化物层的部分以及靠近第一栅极的衬底的部分被去除，以便形成靠近第一栅极的源极和漏极。 接下来，该方法去除氮化物层的剩余部分，包括暴露氧化物层的剩余部分。 去除氮化物层的剩余部分仅暴露氧化物层和源极和漏极凹槽的剩余部分。

    EMBEDDED SILICON GERMANIUM USING A DOUBLE BURIED OXIDE SILICON-ON-INSULATOR WAFER
    10.
    发明申请
    EMBEDDED SILICON GERMANIUM USING A DOUBLE BURIED OXIDE SILICON-ON-INSULATOR WAFER 有权
    嵌入式硅胶锗，使用双层氧化硅绝缘体

    公开(公告)号：US20080265281A1

    公开(公告)日：2008-10-30

    申请号：US12169674

    申请日：2008-07-09

    申请人： Huajie Chen ,  Dureseti Chidambarrao ,  Dominic J. Schepis ,  Henry K. Utomo

    发明人： Huajie Chen ,  Dureseti Chidambarrao ,  Dominic J. Schepis ,  Henry K. Utomo

    IPC分类号： H01L27/12

    CPC分类号： H01L29/7842 ,  H01L27/1203 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848 ,  H01L29/78603 ,  H01L29/78618 ,  H01L29/78684

    摘要： Disclosed is a p-type field effect transistor (pFET) structure and method of forming the pFET. The pFET comprises embedded silicon germanium in the source/drain regions to increase longitudinal stress on the p-channel and, thereby, enhance transistor performance. Increased stress is achieved by increasing the depth of the source/drain regions and, thereby, the volume of the embedded silicon germanium. The greater depth (e.g., up to 100 nm) of the stressed silicon germanium source/drain regions is achieved by using a double BOX SOI wafer. Trenches are etched through a first silicon layer and first buried oxide layer and then the stressed silicon germanium is epitaxially grown from a second silicon layer. A second buried oxide layer isolates the pFET.

    摘要翻译： 公开了一种形成pFET的p型场效应晶体管（pFET）结构和方法。 pFET在源极/漏极区域中包括嵌入的硅锗以增加p沟道上的纵向应力，从而增强晶体管的性能。 通过增加源极/漏极区域的深度，从而增加嵌入式硅锗的体积来实现增加的应力。 通过使用双BOX SOI晶片来实现应力硅锗源极/漏极区域的更大的深度（例如高达100nm）。 通过第一硅层和第一掩埋氧化物层蚀刻沟槽，然后从第二硅层外延生长受应力的硅锗。 第二掩埋氧化物层隔离pFET。