公开(公告)号：US20140212993A1

公开(公告)日：2014-07-31

申请号：US14170100

申请日：2014-01-31

Applicant: Sarin A. Deshpande ,  Sanjeev Aggarwal

Inventor： Sarin A. Deshpande ,  Sanjeev Aggarwal

IPC: H01L43/12

CPC classification number: H01L43/12

Abstract: A method of manufacturing a magnetoresistive-based device includes etching a hard mask layer, the etching having a selectivity greater than 2:1 and preferably less than 5:1 of the hard mask layer to a photo resist thereover. Optionally, the photo resist is trimmed prior to the etch, and oxygen may be applied during or just subsequent to the trim of the photo resist to increase side shrinkage. An additional step includes an oxygen treatment during the etch to remove polymer from the structure and etch chamber.

Abstract translation: 一种制造基于磁阻的器件的方法包括蚀刻硬掩模层，蚀刻具有大于硬掩模层的选择性大于2:1且优选小于5:1的光刻胶。 任选地，在蚀刻之前修整光致抗蚀剂，并且可以在光刻胶的修剪期间期间或之后施加氧气以增加侧收缩。 另外的步骤包括在蚀刻期间从结构和蚀刻室去除聚合物的氧处理。

公开(公告)号：US07723199B2

公开(公告)日：2010-05-25

申请号：US11669759

申请日：2007-01-31

Applicant: Yaw S. Obeng ,  Kezhakkedath R. Udayakumar ,  Scott Robert Summerfelt ,  Sanjeev Aggarwal ,  Francis Gabriel Celii ,  Lindsey H. Hall ,  Robert Kraft ,  Theodore S. Moise

Inventor： Yaw S. Obeng ,  Kezhakkedath R. Udayakumar ,  Scott Robert Summerfelt ,  Sanjeev Aggarwal ,  Francis Gabriel Celii ,  Lindsey H. Hall ,  Robert Kraft ,  Theodore S. Moise

IPC: H01L21/02

CPC classification number: H01L21/02071 ,  H01L21/02129 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02175 ,  H01L21/022 ,  H01L21/02263 ,  H01L21/31683 ,  H01L28/55 ,  H01L28/65

Abstract: A method of manufacturing a semiconductor device is presented. In one aspect, the method comprises forming conductive and ferroelectric material layers on a semiconductor substrate. The material layers are patterned to form electrodes and a ferroelectric layer of a ferroelectric capacitor, wherein a conductive noble metal-containing polymer is generated on sidewalls of the ferroelectric capacitor. The method also comprises converting the conductive noble metal-containing polymer into a non-conducting metal oxide. Converting includes forming a water-soluble metal salt from the conductive noble metal-containing polymer and reacting the water-soluble metal salt with an acqueous acidic solution to form a metal hydroxide. Converting also includes oxidizing the metal hydroxide to form the non-conducting metal oxide.

Abstract translation: 提出了制造半导体器件的方法。 一方面，该方法包括在半导体衬底上形成导电和铁电材料层。 图案化材料层以形成铁电电容器的电极和铁电层，其中在铁电电容器的侧壁上产生导电的含贵金属的聚合物。 该方法还包括将含导电贵金属的聚合物转化为非导电金属氧化物。 转化包括从含导电贵金属的聚合物形成水溶性金属盐，并使水溶性金属盐与酸性水溶液反应，形成金属氢氧化物。 转化还包括氧化金属氢氧化物以形成非导电金属氧化物。

公开(公告)号：US20080076191A1

公开(公告)日：2008-03-27

申请号：US11525475

申请日：2006-09-22

Applicant: Lindsey Hall ,  Sanjeev Aggarwal ,  Satyavolu Srinivas Papa Rao

Inventor： Lindsey Hall ,  Sanjeev Aggarwal ,  Satyavolu Srinivas Papa Rao

IPC: H01L21/8242

CPC classification number: H01L27/11507 ,  H01L27/11502 ,  H01L28/55

Abstract: A ferroelectric capacitor stack is formed over a metal-dielectric interconnect layer. After forming the interconnect layer, the surface of the interconnect layer is treated with gas cluster ion beam (GCIB) processing. Prior to this processing, the surface typically includes metal recesses. The GCIB processing smoothes these recesses and provides a more level surface on which to form the ferroelectric capacitor stack. When the ferroelectric capacitor stack is formed on this leveled surface, leakage is reduced and yields increased as compared to the case where GCIB processing is not used.

Abstract translation: 在金属 - 电介质互连层上形成铁电电容器堆叠。 在形成互连层之后，用气体簇离子束（GCIB）处理处理互连层的表面。 在此处理之前，表面通常包括金属凹槽。 GCIB处理平滑了这些凹槽，并提供了一个更高水平的表面，在其上形成铁电电容器叠层。 当在该平坦化表面上形成铁电电容器堆叠时，与不使用GCIB处理的情况相比，泄漏降低并且产量增加。

公开(公告)号：US07001821B2

公开(公告)日：2006-02-21

申请号：US10705039

申请日：2003-11-10

Applicant: Sanjeev Aggarwal ,  Kelly J. Taylor ,  Theodore S. Moise

Inventor： Sanjeev Aggarwal ,  Kelly J. Taylor ,  Theodore S. Moise

IPC: H01L21/20

CPC classification number: H01L27/11502 ,  H01L21/28568 ,  H01L21/31122 ,  H01L21/32136 ,  H01L21/32139 ,  H01L27/11507 ,  H01L28/55 ,  H01L28/65 ,  H01L28/75

Abstract: Hardmasks and fabrication methods are presented for producing ferroelectric capacitors in a semiconductor device, wherein a hardmask comprising aluminum oxide or strontium tantalum oxide is formed above an upper capacitor electrode material, and capacitor electrode and ferroelectric layers are etched to define a ferroelectric capacitor stack.

Abstract translation: 硬掩模和制造方法用于在半导体器件中制造铁电电容器，其中在上部电容器电极材料上方形成包括氧化铝或氧化钽锶的硬掩模，并蚀刻电容器电极和铁电层以限定铁电电容器叠层。

公开(公告)号：US20050206000A1

公开(公告)日：2005-09-22

申请号：US10805121

申请日：2004-03-19

Applicant: Sanjeev Aggarwal ,  Kelly Taylor ,  Srinivas Raghavan ,  Stephan Grunow ,  Satyavolu Papa Rao

Inventor： Sanjeev Aggarwal ,  Kelly Taylor ,  Srinivas Raghavan ,  Stephan Grunow ,  Satyavolu Papa Rao

IPC: H01L21/285 ,  H01L21/768 ,  H01L21/8242 ,  H01L23/48 ,  H01L23/52 ,  H01L23/532 ,  H01L29/40

CPC classification number: H01L23/53238 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76873 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit copper interconnect structure is formed by forming a dielectric layer (90) over a semiconductor substrate (10). Trenches (110) and vias (120) are formed in the dielectric layer (90) and a barrier layer (130) is formed in the trenches (110) and vias (120) using material such as iridium, iridium oxide, ruthenium, ruthenium oxide, rhodium, rhodium oxide, rhenium, rhenium oxide, platinum, platinum oxide, palladium and palladium oxide. Copper (147) is then used to fill the remaining area in the trenches (110) and vias (120).

Abstract translation: 通过在半导体衬底（10）上形成电介质层（90）形成集成电路铜互连结构。 在电介质层（90）中形成沟槽（110）和通孔（120），并且使用诸如铱，氧化铱，钌，钌的材料在沟槽（110）和通孔（120）中形成阻挡层（130） 氧化物，铑，氧化铑，铼，氧化铼，铂，氧化铂，钯和氧化钯。 铜（147）然后用于填充沟槽（110）和通孔（120）中的剩余区域。

公开(公告)号：US20050101034A1

公开(公告)日：2005-05-12

申请号：US10705039

申请日：2003-11-10

Applicant: Sanjeev Aggarwal ,  Kelly Taylor ,  Theodore Moise

Inventor： Sanjeev Aggarwal ,  Kelly Taylor ,  Theodore Moise

IPC: H01L21/00 ,  H01L21/02 ,  H01L21/285 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/8246 ,  H01L27/115

CPC classification number: H01L27/11502 ,  H01L21/28568 ,  H01L21/31122 ,  H01L21/32136 ,  H01L21/32139 ,  H01L27/11507 ,  H01L28/55 ,  H01L28/65 ,  H01L28/75

Abstract: Hardmasks and fabrication methods are presented for producing ferroelectric capacitors in a semiconductor device, wherein a hardmask comprising aluminum oxide or strontium tantalum oxide is formed above an upper capacitor electrode material, and capacitor electrode and ferroelectric layers are etched to define a ferroelectric capacitor stack.

Abstract translation: 硬掩模和制造方法用于在半导体器件中制造铁电电容器，其中在上部电容器电极材料上方形成包括氧化铝或氧化钽锶的硬掩模，并蚀刻电容器电极和铁电层以限定铁电电容器叠层。

公开(公告)号：US06872669B1

公开(公告)日：2005-03-29

申请号：US10742190

申请日：2003-12-19

Applicant: Scott R. Summerfelt ,  Sanjeev Aggarwal

Inventor： Scott R. Summerfelt ,  Sanjeev Aggarwal

IPC: H01L21/02 ,  H01L21/302 ,  H01L21/314 ,  H01L21/316 ,  H01L21/321 ,  H01L21/3213

CPC classification number: H01L28/55 ,  H01L21/3145 ,  H01L21/31691 ,  H01L21/3212 ,  H01L21/32131 ,  H01L28/65 ,  H01L28/75

Abstract: The present invention is directed to a method of forming a ferroelectric capacitor having a (111) PZT texture. The method includes forming a smooth bottom electrode diffusion barrier layer that facilitates a preferential (111) texture in the subsequently formed bottom electrode layer. The (111) bottom electrode layer texture than facilitates a high quality (111) texture in the overlying PZT layer, thereby improving bit-to-bit polarization charge uniformity for various capacitors as the ferroelectric capacitor sizes continue to shrink.

Abstract translation: 本发明涉及形成具有（111）PZT纹理的铁电电容器的方法。 该方法包括形成平滑的底部电极扩散阻挡层，其有利于随后形成的底部电极层中的优先（111）纹理。 （111）底电极层结构有利于上覆PZT层中的高质量（111）纹理，从而提高了随着铁电电容器尺寸的不断缩小，各种电容器的位对齐极化电荷均匀性。

公开(公告)号：US20050012126A1

公开(公告)日：2005-01-20

申请号：US10620516

申请日：2003-07-16

Applicant: K. Udayakumar ,  Martin Albrecht ,  Theodore Moise ,  Scott Summerfelt ,  Sanjeev Aggarwal ,  Jeff Large

Inventor： K. Udayakumar ,  Martin Albrecht ,  Theodore Moise ,  Scott Summerfelt ,  Sanjeev Aggarwal ,  Jeff Large

IPC: H01L21/02 ,  H01L23/00 ,  H01L29/06 ,  H01L21/00 ,  H01L31/0328 ,  H01L31/0336 ,  H01L31/072

CPC classification number: H01L28/57 ,  H01L23/564 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Semiconductor devices and fabrication methods are presented, in which a hydrogen barrier is provided above a ferroelectric capacitor to prevent degradation of the ferroelectric material during back-end manufacturing processes employing hydrogen. The hydrogen barrier comprises silicon rich silicon oxide or amorphous silicon, which can be used in combination with an aluminum oxide layer to inhibit diffusion of process-related hydrogen into the ferroelectric capacitor layer.

Abstract translation: 提出了半导体器件和制造方法，其中在铁电电容器上方设置氢气阻挡层，以防止在使用氢的后端制造工艺期间铁电材料的劣化。 氢势垒包括富硅氧化物或非晶硅，其可以与氧化铝层组合使用以抑制工艺相关氢扩散到铁电电容器层中。

公开(公告)号：US06686236B2

公开(公告)日：2004-02-03

申请号：US10036827

申请日：2001-12-21

Applicant: Sanjeev Aggarwal ,  Stephen R. Gilbert ,  Scott R. Summerfelt

Inventor： Sanjeev Aggarwal ,  Stephen R. Gilbert ,  Scott R. Summerfelt

IPC: H01L218242

CPC classification number: H01L21/02197 ,  C23C14/08 ,  H01L21/02271 ,  H01L21/31691 ,  H01L28/55 ,  H01L28/56 ,  H01L28/60 ,  H01L28/75

Abstract: A method of fabricating a ferroelectric capacitor is disclosed. The method comprises the decreases a reduction in a bottom electrode material during formation of the ferroelectric dielectric portion of the capacitor. In the above manner, a fatigue resistance of the ferroelectric capacitor is increased substantially.

Abstract translation: 公开了一种制造铁电电容器的方法。 该方法包括在形成电容器的铁电介质部分期间降低底部电极材料的减少。 以上述方式，铁电电容器的耐疲劳性大幅度提高。

公开(公告)号：US06635498B2

公开(公告)日：2003-10-21

申请号：US10222718

申请日：2002-08-16

Applicant: Scott R. Summerfelt ,  Guoqiang Xing ,  Luigi Colombo ,  Sanjeev Aggarwal ,  Theodore S. Moise, IV

Inventor： Scott R. Summerfelt ,  Guoqiang Xing ,  Luigi Colombo ,  Sanjeev Aggarwal ,  Theodore S. Moise, IV

IPC: H01L2100

CPC classification number: H01L27/11502 ,  H01L21/31122 ,  H01L21/32136 ,  H01L27/11507 ,  H01L28/55 ,  H01L28/60

Abstract: A method of fabricating a ferroelectric capacitor is disclosed. The method comprises the patterning of a top electrode layer and a dielectric layer to form a capacitor stack structure having sidewalls associated therewith. Prior to patterning the bottom electrode layer, a protective film is formed on the sidewalls of the capacitor stack structure in order to protect the dielectric material from conductive contaminants associated with a subsequent patterning of the bottom electrode layer.

Abstract translation: 公开了一种制造铁电电容器的方法。 该方法包括图案化顶部电极层和电介质层以形成具有与其相关联的侧壁的电容器堆叠结构。 在图形化底部电极层之前，在电容器堆叠结构的侧壁上形成保护膜，以保护电介质材料免受与随后的底部电极层的图案化有关的导电污染物的影响。