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    Method of Forming a FET Having Ultra-low On-resistance and Low Gate Charge
    1.
    发明申请
    Method of Forming a FET Having Ultra-low On-resistance and Low Gate Charge 有权
    形成具有超低导通电阻和低栅极电荷的FET的方法

    公开(公告)号：US20100258864A1

    公开(公告)日：2010-10-14

    申请号：US12821590

    申请日：2010-06-23

    申请人： Izak Bencuya ,  Brian Sze-Ki Mo ,  Ashok Challa

    发明人： Izak Bencuya ,  Brian Sze-Ki Mo ,  Ashok Challa

    IPC分类号： H01L29/78 ,  H01L21/336

    CPC分类号： H01L29/7813 ,  H01L29/0847 ,  H01L29/42368

    摘要： In accordance with an exemplary embodiment of the invention, a substrate of a first conductivity type silicon is provided. A substrate cap region of the first conductivity type silicon is formed such that a junction is formed between the substrate cap region and the substrate. A body region of a second conductivity type silicon is formed such that a junction is formed between the body region and the substrate cap region. A trench extending through at least the body region is then formed. A source region of the first conductivity type is then formed in an upper portion of the body region. An out-diffusion region of the first conductivity type is formed in a lower portion of the body region as a result of one or more temperature cycles such that a spacing between the source region and the out-diffusion region defines a channel length of the field effect transistor.

    摘要翻译： 根据本发明的示例性实施例，提供了第一导电型硅的衬底。 形成第一导电型硅的衬底帽区域，使得在衬底帽区域和衬底之间形成结。 形成第二导电型硅的体区，使得在体区和衬底帽区之间形成接合部。 然后形成至少延伸穿过身体区域的沟槽。 然后在身体区域的上部形成第一导电类型的源极区域。 作为一个或多个温度循环的结果，第一导电类型的扩散区形成在体区的下部，使得源极区域和外扩散区域之间的间隔限定了场的沟道长度 效应晶体管。

    Method of manufacturing a trench transistor having a heavy body region
    3.
    发明授权
    Method of manufacturing a trench transistor having a heavy body region 有权
    制造具有重体区域的沟槽晶体管的方法

    公开(公告)号：US07696571B2

    公开(公告)日：2010-04-13

    申请号：US12329509

    申请日：2008-12-05

    申请人： Brian Sze-Ki Mo ,  Duc Chau ,  Steven Sapp ,  Izak Bencuya ,  Dean E. Probst

    发明人： Brian Sze-Ki Mo ,  Duc Chau ,  Steven Sapp ,  Izak Bencuya ,  Dean E. Probst

    IPC分类号： H01L29/78

    CPC分类号： H01L29/7813 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/0869 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/66734 ,  H01L29/7811

    摘要： A trenched field effect transistor is provided that includes (a) a semiconductor substrate, (b) a trench extending a predetermined depth into the semiconductor substrate, (c) a pair of doped source junctions, positioned on opposite sides of the trench, (d) a doped heavy body positioned adjacent each source junction on the opposite side of the source junction from the trench, the deepest portion of the heavy body extending less deeply into said semiconductor substrate than the predetermined depth of the trench, and (e) a doped well surrounding the heavy body beneath the heavy body.

    摘要翻译： 提供了沟槽场效应晶体管，其包括（a）半导体衬底，（b）在半导体衬底中延伸预定深度的沟槽，（c）位于沟槽相对侧上的一对掺杂源极结（d ）掺杂的重体，其位于与沟槽的源极结的相对侧上的每个源极结附近，重体的最深部分比沟槽的预定深度更深地延伸到所述半导体衬底中，以及（e）掺杂 很好地围着沉重的身体下面的沉重的身体。

    Trench forming process and integrated circuit device including a trench
    5.
    发明授权
    Trench forming process and integrated circuit device including a trench 失效
    沟槽成形工艺和包括沟槽的集成电路器件

    公开(公告)号：US6103635A

    公开(公告)日：2000-08-15

    申请号：US959197

    申请日：1997-10-28

    申请人： Duc Q Chau ,  Brian Sze-Ki Mo ,  Teina L. Pardue

    发明人： Duc Q Chau ,  Brian Sze-Ki Mo ,  Teina L. Pardue

    IPC分类号： H01L21/3065 ,  H01L21/762 ,  H01L21/76

    CPC分类号： H01L21/76224 ,  H01L21/3065

    摘要： A process for forming a trench in a semiconductor material is provided. The process includes (a) providing a semiconductor substrate, a first mask layer adjacent the surface of the semiconductor substrate, and a second mask layer adjacent the surface of the first mask layer, the second mask layer defining a first open area and the first mask layer defining a second open area that is larger than the first open area and aligned therewith in a manner so that in the area of the openings the first mask layer is undercut with respect to the second mask layer; and (b) removing a portion of the semiconductor substrate through the open area defined by the second mask layer to form a trench in said semiconductor substrate. An IC device formed using the process is also provided.

    摘要翻译： 提供了一种在半导体材料中形成沟槽的工艺。 该方法包括（a）提供半导体衬底，邻近半导体衬底的表面的第一掩模层和与第一掩模层的表面相邻的第二掩模层，第二掩模层限定第一开放区域和第一掩模 层限定第二开放区域，该第二开放区域大于第一开放区域并且以使得在开口区域中的第一掩模层相对于第二掩模层被切削的方式对齐; 和（b）通过由第二掩模层限定的开放区域去除半导体衬底的一部分，以在所述半导体衬底中形成沟槽。 还提供了使用该方法形成的IC器件。

    Method of forming a FET having ultra-low on-resistance and low gate charge
    6.
    发明授权
    Method of forming a FET having ultra-low on-resistance and low gate charge 有权
    形成具有超低导通电阻和低栅极电荷的FET的方法

    公开(公告)号：US07745289B2

    公开(公告)日：2010-06-29

    申请号：US10997818

    申请日：2004-11-24

    申请人： Izak Bencuya ,  Brian Sze-Ki Mo ,  Ashok Challa

    发明人： Izak Bencuya ,  Brian Sze-Ki Mo ,  Ashok Challa

    IPC分类号： H01L21/336

    CPC分类号： H01L29/7813 ,  H01L29/0847 ,  H01L29/42368

    摘要： In accordance with an exemplary embodiment of the invention, a substrate of a first conductivity type silicon is provided. A substrate cap region of the first conductivity type silicon is formed such that a junction is formed between the substrate cap region and the substrate. A body region of a second conductivity type silicon is formed such that a junction is formed between the body region and the substrate cap region. A trench extending through at least the body region is then formed. A source region of the first conductivity type is then formed in an upper portion of the body region. An out-diffusion region of the first conductivity type is formed in a lower portion of the body region as a result of one or more temperature cycles such that a spacing between the source region and the out-diffusion region defines a channel length of the field effect transistor.

    摘要翻译： 根据本发明的示例性实施例，提供了第一导电型硅的衬底。 形成第一导电型硅的衬底帽区域，使得在衬底帽区域和衬底之间形成结。 形成第二导电型硅的体区，使得在体区和衬底帽区之间形成接合部。 然后形成至少延伸穿过身体区域的沟槽。 然后在身体区域的上部形成第一导电类型的源极区域。 作为一个或多个温度循环的结果，第一导电类型的扩散区形成在体区的下部，使得源极区域和外扩散区域之间的间隔限定了场的沟道长度 效应晶体管。

    Method of forming a trench transistor having a superior gate dielectric
    8.
    发明授权
    Method of forming a trench transistor having a superior gate dielectric 失效
    形成具有优良栅极电介质的沟槽晶体管的方法

    公开(公告)号：US06927134B2

    公开(公告)日：2005-08-09

    申请号：US10077258

    申请日：2002-02-14

    申请人： Brian Sze-Ki Mo ,  Duc Chau

    发明人： Brian Sze-Ki Mo ,  Duc Chau

    IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L29/51 ,  H01L29/78 ,  H01L21/8242

    CPC分类号： H01L29/7813 ,  H01L21/28202 ,  H01L21/28211 ,  H01L29/513 ,  H01L29/518

    摘要： A trench transistor with lower leakage current and higher gate rupture voltage. The gate oxide layer of a trench transistor is grown at a temperature above about 1100° C. to reduce thinning of the oxide layer at the corners of the trench. In a further embodiment, a conformal layer of silicon nitride is deposited over the high-temperature oxide layer, and a second oxide layer is formed between the silicon nitride layer and the gate polysilicon. The first gate oxide layer, silicon nitride layer, and second oxide layer form a composite gate dielectric structure that substantially reduces leakage current in trench field effect transistors.

    摘要翻译： 具有较低漏电流和较高栅极断裂电压的沟槽晶体管。 沟槽晶体管的栅极氧化层在高于约1100℃的温度下生长，以减小沟槽角部处的氧化物层的变薄。 在另一个实施例中，在高温氧化物层上沉积氮化硅保形层，并且在氮化硅层和栅极多晶硅之间形成第二氧化物层。 第一栅极氧化物层，氮化硅层和第二氧化物层形成复合栅极电介质结构，其大大减小了沟槽场效应晶体管中的漏电流。

    Method of manufacturing a field effect transistor
    9.
    发明授权
    Method of manufacturing a field effect transistor 失效
    制造场效应晶体管的方法

    公开(公告)号：US06521497B2

    公开(公告)日：2003-02-18

    申请号：US09854102

    申请日：2001-05-09

    申请人： Brian Sze-Ki Mo

    发明人： Brian Sze-Ki Mo

    IPC分类号： H01L21336

    CPC分类号： H01L29/7813 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/0869 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/66734 ,  H01L29/7811

    摘要： A method of manufacturing a trenched field effect transistor that includes a heavy body structure. The method includes forming a plurality of trenches into a semiconductor substrate having dopants of a first conductivity type, wherein the gate electrode of the transistor is formed. A doped well having dopants of a second conductivity type is formed into the substrate and between the trenches. Source regions having dopants of the first conductivity type are formed inside the doped well adjacent to and on opposite sides of the trenches. A heavy body region having dopants of the second conductivity type is formed inside each doped well and at a depth that is shallower than the doped well. The heavy body is formed in a manner that makes an abrupt junction between the heavy body and the well. In one embodiment, the abrupt junction is formed by a dobule implant process.

    摘要翻译： 一种制造包括重体结构的沟槽场效应晶体管的方法。 该方法包括在具有第一导电类型的掺杂剂的半导体衬底中形成多个沟槽，其中形成晶体管的栅电极。 具有第二导电类型的掺杂剂的掺杂阱形成在衬底中并且在沟槽之间。 具有第一导电类型的掺杂剂的源区形成在与沟槽相邻并相邻两侧的掺杂阱内部。 在每个掺杂的阱内部和在比掺杂阱浅的深度处形成具有第二导电类型的掺杂剂的重体区域。 沉重的身体形成在重体和井之间突然连接的方式。 在一个实施例中，通过多臂植入工艺形成突变结。

    Trench transistor with superior gate dielectric
    10.
    发明授权
    Trench transistor with superior gate dielectric 失效
    具有优异栅极电介质的沟槽晶体管

    公开(公告)号：US06404007B1

    公开(公告)日：2002-06-11

    申请号：US09286168

    申请日：1999-04-05

    申请人： Brian Sze-Ki Mo ,  Duc Chau

    发明人： Brian Sze-Ki Mo ,  Duc Chau

    IPC分类号： H01L29792

    CPC分类号： H01L29/7813 ,  H01L21/28202 ,  H01L21/28211 ,  H01L29/513 ,  H01L29/518

    摘要： A trench transistor with lower leakage current and higher gate rupture voltage. The gate oxide layer of a trench transistor is grown at a temperature above about 1100° C. to reduce thinning of the oxide layer at the corners of the trench. In a further embodiment, a conformal layer of silicon nitride is deposited over the high-temperature oxide layer, and a second oxide layer is formed between the silicon nitride layer and the gate polysilicon. The first gate oxide layer, silicon nitride layer, and second oxide layer form a composite gate dielectric structure that substantially reduces leakage current in trench field effect transistors.

    摘要翻译： 具有较低漏电流和较高栅极断裂电压的沟槽晶体管。 沟槽晶体管的栅极氧化层在高于约1100℃的温度下生长，以减小沟槽角部处的氧化物层的变薄。 在另一实施例中，在高温氧化物层上沉积氮化硅保形层，并且在氮化硅层和栅极多晶硅之间形成第二氧化物层。 第一栅极氧化物层，氮化硅层和第二氧化物层形成复合栅极电介质结构，其大大减小了沟槽场效应晶体管中的漏电流。