公开(公告)号：US5212398A

公开(公告)日：1993-05-18

申请号：US931510

申请日：1992-08-21

申请人： Taira Matsunaga ,  Bunshiro Yamaki

发明人： Taira Matsunaga ,  Bunshiro Yamaki

IPC分类号： H01L27/02

CPC分类号： H01L27/0248 ,  H01L27/0255 ,  H01L2924/0002

摘要： In an integrated circuit device including a bipolar transistor, MOSFET, and protective diode for the MOSFET, all formed over a semiconductor substrate, the protective diode for holding an adequate electrostatic breakdown voltage for a gate oxide layer of the MOSFET is provided by forming a second conductivity type buried area continuous with, and in contact with, a second conductivity type region at a boundary between the first conductivity type semiconductor substrate and a first conductivity type second semiconductor layer. By doing so, a substantive junction depth Xj is made deeper as a whole with respect to the second conductivity type region. It is, therefore, possible to obtain a protective diode of adequate electrostatic breakdown-voltage characteristic which does not adversely affect the operation of the MOSFET even if a relatively thin semiconductor layer is employed. The resultant integrated circuit device equipped with the aforementioned protective diode can reveal an improved high frequency characteristic.

摘要翻译： 在包括用于MOSFET的双极晶体管，MOSFET和用于MOSFET的保护二极管的集成电路器件中，全部形成在半导体衬底上，用于保持用于MOSFET的栅极氧化物层的适当静电击穿电压的保护二极管是通过形成第二 在第一导电型半导体衬底和第一导电类型的第二半导体层之间的边界处与第二导电类型区域连续并接触的导电型掩埋区域。 通过这样做，相对于第二导电类型区域，实质上的结深度Xj整体更深。 因此，即使采用相对薄的半导体层，也可以获得足够的静电击穿电压特性的保护二极管，其不会对MOSFET的操作产生不利影响。 具有上述保护二极管的所得集成电路器件可以显示出改进的高频特性。

公开(公告)号：US5283459A

公开(公告)日：1994-02-01

申请号：US812848

申请日：1991-12-20

申请人： Hirokazu Hirano ,  Bunshiro Yamaki

发明人： Hirokazu Hirano ,  Bunshiro Yamaki

IPC分类号： G01P15/08 ,  G01P15/12 ,  H01L29/66 ,  H01L29/84 ,  H01L29/96

CPC分类号： G01P15/123 ,  G01P15/08

摘要： A semiconductor sensor with a compact structure is provided, which comprises a semiconductor substrate, a semiconductor diaphragm integrally formed with the semiconductor substrate, and a penetrating aperture formed in the semiconductor substrate so as to surround desired sides of the diaphragm. The aperture has first and second funnel-shaped aperatures whose intersecting conic sections open toward opposite directions. A cavity for defining the diaphragm is provided when the semiconductor substrate is subjected to electrolytic etching to form the second funnel-shaped aperture therein.

摘要翻译： 提供具有紧凑结构的半导体传感器，其包括半导体衬底，与半导体衬底一体形成的半导体膜，以及形成在半导体衬底中以围绕隔膜的所需侧的穿透孔。 该孔具有第一和第二漏斗形的温度，其相交的锥形部分向相反的方向敞开。 当半导体衬底经受电解蚀刻以在其中形成第二漏斗形孔时，提供用于限定隔膜的空腔。

公开(公告)号：US4962056A

公开(公告)日：1990-10-09

申请号：US293283

申请日：1989-01-04

申请人： Bunshiro Yamaki ,  Nobutaka Matsuoka

发明人： Bunshiro Yamaki ,  Nobutaka Matsuoka

IPC分类号： H01L21/304 ,  H01L21/762

CPC分类号： H01L21/76297 ,  Y10S148/012 ,  Y10S438/928 ,  Y10S438/977

摘要： According to the method of the present invention of manufacturing, from a semiconductor wafer, a dielectric substrate including insulated and separated island regions, a silicon oxide film is formed on a surface of a monocrystalline semiconductor wafer, and a mask consisting of a frame portion spreading on a peripheral region of the wafer and a grid-like portion arranged within the frame portion is formed. Then, in a patterning step, the surface of the wafer is exposed with the frame portion and the grid-like portion of the mask being left. Separation grooves arranged in a grid-like manner are formed in the exposed surface by etching. After a silicon oxide film is formed on the surfaces of the grooves, a polycrystalline semiconductor layer is made to grow on the silicon oxide film formed on the surfaces of the grooves and on the silicon oxide film formed on the surface of the wafer. The resultant structure is lapped from the side of the surface of the wafer such that the structure has a predetermined thickness as measured from a reference plane defined in the polycrystalline semiconductor layer, thus forming a plurality of island regions divided by the separation grooves.

摘要翻译： 根据本发明的制造方法，从半导体晶片形成包括绝缘和分离的岛状区域的电介质基板，在单晶半导体晶片的表面上形成氧化硅膜，由掩模 在晶片的周边区域上形成有布置在框架部分内的格栅状部分。 然后，在图案化步骤中，晶片的表面暴露于框架部分，并且掩模的栅格状部分被留下。 通过蚀刻在暴露的表面上形成格栅状布置的分隔槽。 在沟槽的表面上形成氧化硅膜之后，使多晶半导体层在形成于沟槽表面上的氧化硅膜上和在晶片表面形成的氧化硅膜上生长。 所得到的结构从晶片表面的一侧重叠，使得结构具有从多晶半导体层中限定的参考平面测量的预定厚度，从而形成由分离槽分隔的多个岛状区域。

公开(公告)号：US5238850A

公开(公告)日：1993-08-24

申请号：US903741

申请日：1992-06-25

申请人： Taira Matsunaga ,  Bunshiro Yamaki

发明人： Taira Matsunaga ,  Bunshiro Yamaki

IPC分类号： H01L21/8249 ,  H01L23/29 ,  H01L27/06

CPC分类号： H01L23/298 ,  H01L21/8249 ,  H01L27/0635 ,  H01L2924/0002 ,  H01L2924/13091

摘要： A Bi-MOS type semiconductor integrated circuit device having at least one bipolar transistor in an island region is provided. The island region is covered with a multilayer insulating film which is formed of a silicon oxide film and a silicon nitride film having a different etching resistance with each other. Collector and base contact holes and an intended emitter contact hole are formed in the multilayer insulating film at the same time to provide bipolar transistors having a fine structure. An insulated gate MOS transistor includes a protective film such as polysilicon film covering a gate insulating film to increase the reliability.

摘要翻译： 提供了一种在岛状区域中具有至少一个双极晶体管的Bi-MOS型半导体集成电路器件。 岛状区域覆盖有由氧化硅膜和具有不同的耐蚀刻性的氮化硅膜形成的多层绝缘膜。 在多层绝缘膜中同时形成集电极和基极接触孔和预期的发射极接触孔，以提供具有精细结构的双极晶体管。 绝缘栅极MOS晶体管包括覆盖栅极绝缘膜的保护膜，例如多晶硅膜，以提高可靠性。

公开(公告)号：US5100812A

公开(公告)日：1992-03-31

申请号：US625474

申请日：1990-12-11

申请人： Yoshiki Yamada ,  Bunshiro Yamaki

发明人： Yoshiki Yamada ,  Bunshiro Yamaki

IPC分类号： H01L29/73 ,  H01L21/331 ,  H01L23/482 ,  H01L29/732

CPC分类号： H01L29/66303 ,  H01L23/4824 ,  H01L29/66272 ,  H01L2924/0002 ,  Y10S148/011 ,  Y10S148/124

摘要： According to a method of manufacturing a high-frequency bipolar transistor, a p-type base region is formed on an n-type silicon substrate. A first oxide film and a nitride film are formed on the base region. A base contact hole is formed by etching, and a first polysilicon film containing a p-type impurity and serving as a base electrode is formed thereon. A second oxide film having a thickness larger than that of the first oxide film is formed by thermal oxidation around the base contact hole to surround the first polysilicon film. A portion of the nitride film which is not covered with said second oxide film and a portion of the first oxide film therebelow are removed by etching to form an emitter contact hole. A second polysilicon film including an n-type impurity and serving as an emitter electrode is formed in the emitter contact hole. The n-type impurity in the second polysilicon film is diffused in the substrate by annealing to form an n-type emitter region. In the completed bipolar transistor, the base electrode and the emitter electrode are insulated from each other by the second oxide film.

公开(公告)号：US5021859A

公开(公告)日：1991-06-04

申请号：US436056

申请日：1989-11-09

申请人： Takahiro Ito ,  Bunshiro Yamaki ,  Yoshio Yamamoto

发明人： Takahiro Ito ,  Bunshiro Yamaki ,  Yoshio Yamamoto

IPC分类号： H01L29/73 ,  H01L21/331 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/732

CPC分类号： H01L27/0623

摘要： In a high-frequency amplifying semiconductor device in which a MOS field effect transistor and a bipolar transistor are formed within the same wafer and a source electrode of the MOS field effect transistor is connected to a lead frame by a bonding wire, use is made of a wafer for fabricating the MOS field effect transistor and the bipolar transistor, in which on a semiconductor substrate of P++ type is formed a first epitaxial layer of P or P- type, a buried layer of N+ type is formed in the first epitaxial layer of the first conductivity type and a second epitaxial layer of P type is formed on the buried layer and the first epitaxial layer. The use of such a wafer, which has no P- type Si substrate, allows the source resistance of the MOS field effect transistor to be decreased. The high-frequency amplifying semiconductor device is improved in high-frequency gain and NF.

摘要翻译： 在同一晶片内形成MOS场效应晶体管和双极晶体管的高频放大半导体器件中，MOS场效应晶体管的源电极通过接合线与引线框架连接，使用 用于制造MOS场效应晶体管和双极晶体管的晶片，其中在P ++型半导体衬底上形成P型或P-型第一外延层，在第一外延层中形成N +型掩埋层 第一导电类型和第二外延层P型形成在掩埋层和第一外延层上。 不使用P-型Si衬底的这种晶片的使用允许MOS场效应晶体管的源极电阻降低。 高频放大半导体器件在高频增益和NF方面得到了改善。

公开(公告)号：US4680569A

公开(公告)日：1987-07-14

申请号：US654940

申请日：1984-09-27

申请人： Bunshiro Yamaki ,  Sadatake Kikuchi ,  Yutaka Tomisawa

发明人： Bunshiro Yamaki ,  Sadatake Kikuchi ,  Yutaka Tomisawa

IPC分类号： G01L9/04 ,  G01L9/00 ,  H01L29/84 ,  G01L1/22

CPC分类号： G01L19/0084 ,  G01L19/147

摘要： A semiconductor pressure sensor wherein a semiconductor chip of diaphragm type is supported by a mount plate through a thin tubular supporting member or a pressure inlet tube having a coefficient of thermal expansion similar to that of a substrate constituting the semiconductor chip. The semiconductor chip is fixed to the thin tubular supporting member or the pressure inlet tube by means of a bonding material, and the thin tubular supporting member or the pressure inlet tube is fixed by means of a bonding material having a high bonding strength with respect thereto, thus absorbing thermal stress produced due to the difference in coefficient of thermal expansion.

摘要翻译： 一种半导体压力传感器，其中隔膜型半导体芯片通过薄管状支撑构件或具有类似于构成半导体芯片的衬底的热膨胀系数的压力入口管由安装板支撑。 半导体芯片通过接合材料固定在薄管状支撑构件或压力入口管上，薄壁管状支撑构件或压力入口管借助于相对于其的高粘合强度的接合材料固定 ，从而吸收由于热膨胀系数的差异而产生的热应力。