公开(公告)号：US07460409B2

公开(公告)日：2008-12-02

申请号：US11584589

申请日：2006-10-23

申请人： Bunsho Kuramori

发明人： Bunsho Kuramori

IPC分类号： G11C11/34

CPC分类号： G11C16/28 ,  G11C16/24

摘要： A nonvolatile memory includes a memory cell array in which a plurality of memory cells are connected to a plurality of wordlines and a plurality of bitlines respectively intersecting at a right angle with the plurality of wordlines; a selector for selecting one of the bitlines which is connected to first one of the memory cells in which actual data is stored; and a transfer circuit for connecting with a reference bitline which is connected to second one of the memory cells in which a reference level is stored. The nonvolatile memory further includes an amplifier section, connected to the selector and the transfer circuit, for reading out and amplifying levels of the bitline and the reference bitline and comparing the actual data with the reference level; and a charger for charging the bitline selected by the selector.

摘要翻译： 非易失性存储器包括存储单元阵列，其中多个存储器单元连接到分别与多个字线成直角相交的多个字线和多个位线; 选择器，用于选择连接到存储有实际数据的存储单元中的第一个的位线之一; 以及用于与参考位线连接的传送电路，该参考位线连接到其中存储参考电平的第二存储器单元。 非易失性存储器还包括连接到选择器和传输电路的放大器部分，用于读出和放大位线和参考位线的电平并将实际数据与参考电平进行比较; 以及用于对由选择器选择的位线进行充电的充电器。

公开(公告)号：US20070121379A1

公开(公告)日：2007-05-31

申请号：US11584589

申请日：2006-10-23

申请人： Bunsho Kuramori

发明人： Bunsho Kuramori

IPC分类号： G11C16/04

CPC分类号： G11C16/28 ,  G11C16/24

摘要： A nonvolatile memory includes a memory cell array in which a plurality of memory cells are connected to a plurality of wordlines and a plurality of bitlines respectively intersecting at a right angle with the plurality of wordlines; a selector for selecting one of the bitlines which is connected to first one of the memory cells in which actual data is stored; and a transfer circuit for connecting with a reference bitline which is connected to second one of the memory cells in which a reference level is stored. The nonvolatile memory further includes an amplifier section, connected to the selector and the transfer circuit, for reading out and amplifying levels of the bitline and the reference bitline and comparing the actual data with the reference level; and a charger for charging the bitline selected by the selector.

摘要翻译： 非易失性存储器包括存储单元阵列，其中多个存储器单元连接到分别与多个字线成直角相交的多个字线和多个位线; 选择器，用于选择连接到存储有实际数据的存储单元中的第一个的位线之一; 以及用于与参考位线连接的传送电路，该参考位线连接到其中存储参考电平的第二存储器单元。 非易失性存储器还包括连接到选择器和传输电路的放大器部分，用于读出和放大位线和参考位线的电平并将实际数据与参考电平进行比较; 以及用于对由选择器选择的位线进行充电的充电器。

公开(公告)号：US08854877B2

公开(公告)日：2014-10-07

申请号：US13179206

申请日：2011-07-08

申请人： Yuji Nagashima ,  Bunsho Kuramori ,  Hiroyuki Tanikawa

发明人： Yuji Nagashima ,  Bunsho Kuramori ,  Hiroyuki Tanikawa

IPC分类号： G11C11/34 ,  G11C8/06 ,  G11C16/10 ,  G11C16/04 ,  G11C29/00 ,  G11C17/14

CPC分类号： G11C8/06 ,  G11C16/0475 ,  G11C16/0491 ,  G11C16/10 ,  G11C17/146 ,  G11C29/883

摘要： A nonvolatile semiconductor memory device and a method of reusing the same that allow a good use of the semiconductor device without degrading characteristics even when reused. The semiconductor memory device comprises information holding means for holding information that indicates an operation mode of said memory cell array, a decoder for generating, to said memory cell array, a selection signal to designate at least a read address of said memory cell array in accordance with an address signal that comprises plural bits; and mode setting means for fixing a logical value of at least one bit of said plural bits of said address signal in accordance with the information held by said information holding means, and supplying said address signal, on which fixing of the logical value is effected, to said decoder.

摘要翻译： 一种非易失性半导体存储器件及其再利用方法，即使在再利用时也能够良好地利用半导体器件而不劣化特性。 半导体存储器件包括用于保存指示所述存储单元阵列的操作模式的信息的信息保持装置，用于向所述存储单元阵列生成至少指定所述存储单元阵列的读地址的选择信号的解码器 具有包括多个位的地址信号; 以及模式设定装置，用于根据由所述信息保持装置保存的信息来固定所述地址信号的所述多个比特的至少一个比特的逻辑值，并且提供实现该逻辑值固定的所述地址信号， 到所述解码器。

公开(公告)号：US20120020174A1

公开(公告)日：2012-01-26

申请号：US13186921

申请日：2011-07-20

申请人： Bunsho KURAMORI

发明人： Bunsho KURAMORI

IPC分类号： G11C8/08

CPC分类号： G11C8/08

摘要： Disclosed herein is a semiconductor memory which is capable of performing data reading without a faulty operation irrespective of the span of an address skew period. In detecting whether an address transition has been made and precharging a bit line formed in a memory cell array when a certain delay period has elapsed after the address transition is detected, the delay period is adjusted based on a delay period extension signal.

摘要翻译： 这里公开了一种半导体存储器，其能够执行数据读取而没有故障操作，而与地址偏移周期的跨度无关。 在检测到地址转换是否已经进行并且当在检测到地址转换之后经过了一定延迟时间时，在存储单元阵列中形成的位线预充电时，延迟周期根据延迟周期扩展信号进行调整。

公开(公告)号：US07528641B2

公开(公告)日：2009-05-05

申请号：US11476900

申请日：2006-06-29

申请人： Bunsho Kuramori

发明人： Bunsho Kuramori

IPC分类号： H03H11/26

CPC分类号： H03H11/26

摘要： The present invention provides a delay circuit in which normal CMOS type inverters and modified inverters added with delay PMOSs on the power supply voltage VDD terminal side are alternately cascade-connected. A correction circuit that supplies a control signal to the gates of the delay PMOSs is provided in association with the delay circuit. The correction circuit comprises a PMOS diode-connected in the forward direction, and resistors that connect the drain of the PMOS to the ground voltage VSS terminal side. The correction circuit outputs the control signal from an internal node provided between the resistors. Thus, when a power supply voltage rises, the voltage of the control signal also rises. Hence, gate-to-source voltages of the delay PMOSs are kept constant, and drain currents remain unchanged and a delay time is kept constant as well.

摘要翻译： 本发明提供一种延迟电路，其中在电源电压VDD端侧添加有延迟PMOS的正常CMOS型反相器和改型逆变器交替级联。 与延迟电路相关联地提供向延迟PMOS的栅极提供控制信号的校正电路。 校正电路包括正向连接的PMOS二极管和将PMOS的漏极连接到接地电压VSS端子侧的电阻器。 校正电路从设置在电阻器之间的内部节点输出控制信号。 因此，当电源电压上升时，控制信号的电压也上升。 因此，延迟PMOS的栅极 - 源极电压保持恒定，并且漏极电流保持不变，并且延迟时间也保持恒定。

公开(公告)号：US20080080256A1

公开(公告)日：2008-04-03

申请号：US11902220

申请日：2007-09-20

申请人： Bunsho Kuramori

发明人： Bunsho Kuramori

IPC分类号： G11C16/06 ,  G11C8/18

CPC分类号： G11C7/12 ,  G11C7/22 ,  G11C7/222 ,  G11C16/24 ,  G11C16/30 ,  G11C2207/005

摘要： A semiconductor memory device includes an array of memory cells and an adjustment circuit for adjusting the pulse width of an address transition detect equalizer (ATDEQ) signal. The adjustment circuit receives an address transition detection (ATD) signal and is responsive to the level changes of voltages Vp and Vn to adjust the pulse width of the ATDEQ signal accordingly. The resulting signal ATDEQ is supplied to a power supply circuit for a bit line selector for selecting a bit line of the array of memory cells. The device can thus accomplish the readouts of bit “0” and bit “1” in a state less liable to delay.

摘要翻译： 半导体存储器件包括存储器单元阵列和用于调整地址转换检测均衡器（ATDEQ）信号的脉冲宽度的调整电路。 调整电路接收地址转换检测（ATD）信号，并且响应于电压Vp和Vn的电平变化，以相应地调整ATDEQ信号的脉冲宽度。 得到的信号ATDEQ被提供给用于选择存储器单元阵列的位线的位线选择器的电源电路。 因此，该装置可以在不太可能延迟的状态下完成位“0”和位“1”的读出。

公开(公告)号：US20070008022A1

公开(公告)日：2007-01-11

申请号：US11476900

申请日：2006-06-29

申请人： Bunsho Kuramori

发明人： Bunsho Kuramori

IPC分类号： H03H11/26

CPC分类号： H03H11/26

摘要： The present invention provides a delay circuit in which normal CMOS type inverters and modified inverters added with delay PMOSs on the power supply voltage VDD terminal side are alternately cascade-connected. A correction circuit that supplies a control signal to the gates of the delay PMOSs is provided in association with the delay circuit. The correction circuit comprises a PMOS diode-connected in the forward direction, and resistors that connect the drain of the PMOS to the ground voltage VSS terminal side. The correction circuit outputs the control signal from an internal node provided between the resistors. Thus, when a power supply voltage rises, the voltage of the control signal also rises. Hence, gate-to-source voltages of the delay PMOSs are kept constant, and drain currents remain unchanged and a delay time is kept constant as well.

摘要翻译： 本发明提供一种延迟电路，其中在电源电压VDD端侧添加有延迟PMOS的普通CMOS型反相器和改型逆变器交替级联。 与延迟电路相关联地提供向延迟PMOS的栅极提供控制信号的校正电路。 校正电路包括正向连接的PMOS二极管和将PMOS的漏极连接到接地电压VSS端子侧的电阻器。 校正电路从设置在电阻器之间的内部节点输出控制信号。 因此，当电源电压上升时，控制信号的电压也上升。 因此，延迟PMOS的栅极 - 源极电压保持恒定，并且漏极电流保持不变，并且延迟时间也保持恒定。

公开(公告)号：US07020023B2

公开(公告)日：2006-03-28

申请号：US10964642

申请日：2004-10-15

申请人： Bunsho Kuramori

发明人： Bunsho Kuramori

IPC分类号： G11C16/06

CPC分类号： G11C16/28

摘要： A semiconductor integrated circuit comprises a plurality of memory cell blocks each including a comparing cell which detects a current level and data cells which store data therein, a plurality of reference voltage determining circuits each of which determines a second reference voltage in accordance with a first reference voltage and the output of the comparing cell, and amplifiers each of which compares the data stored in the data cell and the output of the reference voltage determining circuit and amplifies the result of comparison. The outputs of the comparing cells are short-circuited in a predetermined combination. Owing to the configuration of the semiconductor integrated circuit, misdetection of each reading cell due to process variations related to each individual comparing cell can be prevented and yield enhancement can be achieved. Further, such a configuration leads to a cost reduction.

摘要翻译： 半导体集成电路包括多个存储单元块，每个存储单元块包括检测当前电平的比较单元和在其中存储数据的数据单元;多个参考电压确定电路，每个基准电压确定电路根据第一参考值确定第二参考电压 电压和比较单元的输出，以及每个比较存储在数据单元中的数据和参考电压确定电路的输出的放大器，并放大比较结果。 比较单元的输出以预定的组合短路。 由于半导体集成电路的结构，可以防止由于与每个单独比较单元相关的工艺变化引起的每个读取单元的错误检测，并且可以实现提高产量。 此外，这种配置导致成本降低。

公开(公告)号：US08462567B2

公开(公告)日：2013-06-11

申请号：US13186921

申请日：2011-07-20

申请人： Bunsho Kuramori

发明人： Bunsho Kuramori

IPC分类号： G11C7/00

CPC分类号： G11C8/08

摘要： A semiconductor memory which is capable of performing data reading without a faulty operation irrespective of the span of an address skew period. In detecting whether an address transition has been made and precharging a bit line formed in a memory cell array when a certain delay period has elapsed after the address transition is detected, the delay period is adjusted based on a delay period extension signal.

摘要翻译： 一种半导体存储器，能够无故障地执行数据读取，而与地址偏移周期的跨度无关。 在检测到地址转换是否已经进行并且当在检测到地址转换之后经过了一定延迟时间时，在存储单元阵列中形成的位线预充电时，延迟周期根据延迟周期扩展信号进行调整。

公开(公告)号：US20120163075A1

公开(公告)日：2012-06-28

申请号：US13327930

申请日：2011-12-16

申请人： Hiroyuki TANIKAWA ,  Bunsho KURAMORI

发明人： Hiroyuki TANIKAWA ,  Bunsho KURAMORI

IPC分类号： G11C16/06

CPC分类号： G11C7/062 ,  G11C16/24 ,  G11C16/28

摘要： There is provided a non-volatile storage device including: a bit line that is connected to a non-volatile storage element and is applied with a voltage of magnitude corresponding to the logic value stored in the storage element; a charging section that charges the bit line to a voltage of equivalent magnitude to the reference voltage; a voltage generation section that is connected between the reference voltage line and the bit line, comprises a capacitance load for generating coupling charge when charging by the charging section has been performed, and employs the capacitance load to generate a voltage according to a difference between the magnitude of the voltage of the reference voltage line and the magnitude of the voltage of the bit line as a voltage expressing the comparison result; and a charge absorbing section for absorbing the coupling charge generated by the capacitance load.

摘要翻译： 提供了一种非易失性存储装置，包括：位线，其连接到非易失性存储元件，并施加与存储在存储元件中的逻辑值对应的大小的电压; 充电部，其将所述位线充电到与所述参考电压等价的电压; 连接在参考电压线和位线之间的电压产生部分包括用于在由充电部进行充电时产生耦合电荷的电容负载，并且采用电容负载来产生根据 参考电压线的电压的大小和位线的电压的大小作为表示比较结果的电压; 以及用于吸收由电容负载产生的耦合电荷的电荷吸收部分。