公开(公告)号：US20150348982A1

公开(公告)日：2015-12-03

申请号：US14819841

申请日：2015-08-06

Applicant: Jeeyong Kim ,  Woonkyung LEE ,  Sunggil KIM ,  Jin-Kyu KANG ,  Jung-Hwan LEE ,  Bonyoung KOO ,  Kihyun HWANG ,  Byoungsun JU ,  Jintae NOH

Inventor： Jeeyong Kim ,  Woonkyung LEE ,  Sunggil KIM ,  Jin-Kyu KANG ,  Jung-Hwan LEE ,  Bonyoung KOO ,  Kihyun HWANG ,  Byoungsun JU ,  Jintae NOH

IPC: H01L27/115 ,  H01L29/78 ,  H01L23/535

CPC classification number: H01L27/11526 ,  H01L21/28 ,  H01L21/76841 ,  H01L23/48 ,  H01L23/535 ,  H01L27/11521 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/4958 ,  H01L29/78 ,  H01L29/788 ,  H01L29/7883 ,  H01L29/792 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Provided are a semiconductor device and a method of manufacturing the semiconductor device. The semiconductor device includes a charge storage pattern formed on a substrate; a dielectric pattern formed on the charge storage pattern; a first conductive pattern including silicon doped with a first impurity of a first concentration, the first conductive pattern being disposed on the dielectric pattern; and a second conductive pattern including metal silicide doped with a second impurity of a second concentration, the second conductive pattern being disposed on the first conductive pattern. The first concentration may be higher than the second concentration.

公开(公告)号：US08476692B2

公开(公告)日：2013-07-02

申请号：US13037502

申请日：2011-03-01

Applicant: Jeeyong Kim ,  WoonKyung Lee ,  Sunggil Kim ,  Jin-Kyu Kang ,  Jung-Hwan Lee ,  Bonyoung Koo ,  Kihyun Hwang ,  Byoungsun Ju ,  Jintae Noh

Inventor： Jeeyong Kim ,  WoonKyung Lee ,  Sunggil Kim ,  Jin-Kyu Kang ,  Jung-Hwan Lee ,  Bonyoung Koo ,  Kihyun Hwang ,  Byoungsun Ju ,  Jintae Noh

IPC: H01L29/778

CPC classification number: H01L27/11526 ,  H01L21/28 ,  H01L21/76841 ,  H01L23/48 ,  H01L23/535 ,  H01L27/11521 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/4958 ,  H01L29/78 ,  H01L29/788 ,  H01L29/7883 ,  H01L29/792 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Provided are a semiconductor device and a method of manufacturing the semiconductor device. The semiconductor device includes a charge storage pattern formed on a substrate; a dielectric pattern formed on the charge storage pattern; a first conductive pattern including silicon doped with a first impurity of a first concentration, the first conductive pattern being disposed on the dielectric pattern; and a second conductive pattern including metal silicide doped with a second impurity of a second concentration, the second conductive pattern being disposed on the first conductive pattern. The first concentration may be higher than the second concentration.

Abstract translation: 提供半导体器件和制造半导体器件的方法。 半导体器件包括形成在衬底上的电荷存储图案; 形成在电荷存储图案上的电介质图案; 第一导电图案，包括掺杂有第一浓度的第一杂质的硅，所述第一导电图案设置在所述电介质图案上; 以及第二导电图案，其包括掺杂有第二浓度的第二杂质的金属硅化物，所述第二导电图案设置在所述第一导电图案上。 第一浓度可能高于第二浓度。

公开(公告)号：US20110215392A1

公开(公告)日：2011-09-08

申请号：US13037502

申请日：2011-03-01

Applicant: Jeeyong Kim ,  WoonKyung Lee ,  Sunggil Kim ,  Jin-Kyu Kang ,  Jung-Hwan Lee ,  Bonyoung Koo ,  Kihyun Hwang ,  Byoungsun Ju ,  Jintae Noh

Inventor： Jeeyong Kim ,  WoonKyung Lee ,  Sunggil Kim ,  Jin-Kyu Kang ,  Jung-Hwan Lee ,  Bonyoung Koo ,  Kihyun Hwang ,  Byoungsun Ju ,  Jintae Noh

IPC: H01L29/788 ,  H01L21/28 ,  H01L23/48 ,  H01L29/792

CPC classification number: H01L27/11526 ,  H01L21/28 ,  H01L21/76841 ,  H01L23/48 ,  H01L23/535 ,  H01L27/11521 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/4958 ,  H01L29/78 ,  H01L29/788 ,  H01L29/7883 ,  H01L29/792 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Provided are a semiconductor device and a method of manufacturing the semiconductor device. The semiconductor device includes a charge storage pattern formed on a substrate; a dielectric pattern formed on the charge storage pattern; a first conductive pattern including silicon doped with a first impurity of a first concentration, the first conductive pattern being disposed on the dielectric pattern; and a second conductive pattern including metal silicide doped with a second impurity of a second concentration, the second conductive pattern being disposed on the first conductive pattern. The first concentration may be higher than the second concentration.

Abstract translation: 提供半导体器件和制造半导体器件的方法。 半导体器件包括形成在衬底上的电荷存储图案; 形成在电荷存储图案上的电介质图案; 第一导电图案，包括掺杂有第一浓度的第一杂质的硅，所述第一导电图案设置在所述电介质图案上; 以及第二导电图案，其包括掺杂有第二浓度的第二杂质的金属硅化物，所述第二导电图案设置在所述第一导电图案上。 第一浓度可能高于第二浓度。

公开(公告)号：US20110001181A1

公开(公告)日：2011-01-06

申请号：US12829689

申请日：2010-07-02

Applicant: Byoungsun Ju ,  Sunggil Kim ,  Jintae Noh ,  Siyoung Choi ,  Kihyun Hwang

Inventor： Byoungsun Ju ,  Sunggil Kim ,  Jintae Noh ,  Siyoung Choi ,  Kihyun Hwang

IPC: H01L27/115 ,  H01L29/788

CPC classification number: H01L29/7883 ,  H01L21/28273 ,  H01L27/11521 ,  H01L29/42324 ,  H01L29/4916 ,  H01L29/66825

Abstract: Provided is a nonvolatile memory device. The nonvolatile memory device includes: a tunnel insulation layer on a semiconductor substrate; a floating gate electrode including a bottom gate electrode doped with carbon and contacting the tunnel insulation layer and a top gate electrode on the bottom gate electrode; a gate interlayer insulation layer on the floating gate electrode; and a control gate electrode on the gate interlayer insulation layer.

Abstract translation: 提供了一种非易失性存储器件。 非易失性存储器件包括：半导体衬底上的隧道绝缘层; 包括掺杂有碳并与隧道绝缘层接触的底栅电极和底栅电极上的顶栅电极的浮栅电极; 浮栅电极上的栅极层间绝缘层; 以及栅极层间绝缘层上的控制栅电极。

公开(公告)号：US20150145018A1

公开(公告)日：2015-05-28

申请号：US14568737

申请日：2014-12-12

Applicant: Jeeyong Kim ,  Woonkyung Lee ,  Sunggil Kim ,  Jin-Kyu Kang ,  Jung-Hwan Lee ,  Bonyoung Koo ,  Kihyun Hwang ,  Byoungsun Ju ,  Jintae Noh

Inventor： Jeeyong Kim ,  Woonkyung Lee ,  Sunggil Kim ,  Jin-Kyu Kang ,  Jung-Hwan Lee ,  Bonyoung Koo ,  Kihyun Hwang ,  Byoungsun Ju ,  Jintae Noh

IPC: H01L29/49 ,  H01L27/115 ,  H01L29/788

CPC classification number: H01L27/11526 ,  H01L21/28 ,  H01L21/76841 ,  H01L23/48 ,  H01L23/535 ,  H01L27/11521 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/4958 ,  H01L29/78 ,  H01L29/788 ,  H01L29/7883 ,  H01L29/792 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Provided are a semiconductor device and a method of manufacturing the semiconductor device. The semiconductor device includes a charge storage pattern formed on a substrate; a dielectric pattern formed on the charge storage pattern; a first conductive pattern including silicon doped with a first impurity of a first concentration, the first conductive pattern being disposed on the dielectric pattern; and a second conductive pattern including metal silicide doped with a second impurity of a second concentration, the second conductive pattern being disposed on the first conductive pattern. The first concentration may be higher than the second concentration.

Abstract translation: 提供半导体器件和制造半导体器件的方法。 半导体器件包括形成在衬底上的电荷存储图案; 形成在电荷存储图案上的电介质图案; 第一导电图案，包括掺杂有第一浓度的第一杂质的硅，所述第一导电图案设置在所述电介质图案上; 以及第二导电图案，其包括掺杂有第二浓度的第二杂质的金属硅化物，所述第二导电图案设置在所述第一导电图案上。 第一浓度可能高于第二浓度。

公开(公告)号：US08232590B2

公开(公告)日：2012-07-31

申请号：US12829689

申请日：2010-07-02

Applicant: Byoungsun Ju ,  Sunggil Kim ,  Jintae Noh ,  Siyoung Choi ,  Kihyun Hwang

Inventor： Byoungsun Ju ,  Sunggil Kim ,  Jintae Noh ,  Siyoung Choi ,  Kihyun Hwang

IPC: H01L29/788

CPC classification number: H01L29/7883 ,  H01L21/28273 ,  H01L27/11521 ,  H01L29/42324 ,  H01L29/4916 ,  H01L29/66825

Abstract: Provided is a nonvolatile memory device. The nonvolatile memory device includes: a tunnel insulation layer on a semiconductor substrate; a floating gate electrode including a bottom gate electrode doped with carbon and contacting the tunnel insulation layer and a top gate electrode on the bottom gate electrode; a gate interlayer insulation layer on the floating gate electrode; and a control gate electrode on the gate interlayer insulation layer.

Abstract translation: 提供了一种非易失性存储器件。 非易失性存储器件包括：半导体衬底上的隧道绝缘层; 包括掺杂有碳并与隧道绝缘层接触的底栅电极和底栅电极上的顶栅电极的浮栅电极; 浮栅电极上的栅极层间绝缘层; 以及栅极层间绝缘层上的控制栅电极。

公开(公告)号：US09443863B2

公开(公告)日：2016-09-13

申请号：US14819841

申请日：2015-08-06

Applicant: Jeeyong Kim ,  Woonkyung Lee ,  Sunggil Kim ,  Jin-Kyu Kang ,  Jung-Hwan Lee ,  Bonyoung Koo ,  Kihyun Hwang ,  Byoungsun Ju ,  Jintae Noh

Inventor： Jeeyong Kim ,  Woonkyung Lee ,  Sunggil Kim ,  Jin-Kyu Kang ,  Jung-Hwan Lee ,  Bonyoung Koo ,  Kihyun Hwang ,  Byoungsun Ju ,  Jintae Noh

IPC: H01L29/49 ,  H01L27/115 ,  H01L23/535 ,  H01L29/78 ,  H01L21/28 ,  H01L23/48 ,  H01L29/788 ,  H01L29/792 ,  H01L21/768

CPC classification number: H01L27/11526 ,  H01L21/28 ,  H01L21/76841 ,  H01L23/48 ,  H01L23/535 ,  H01L27/11521 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/4958 ,  H01L29/78 ,  H01L29/788 ,  H01L29/7883 ,  H01L29/792 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Provided are a semiconductor device and a method of manufacturing the semiconductor device. The semiconductor device includes a charge storage pattern formed on a substrate; a dielectric pattern formed on the charge storage pattern; a first conductive pattern including silicon doped with a first impurity of a first concentration, the first conductive pattern being disposed on the dielectric pattern; and a second conductive pattern including metal silicide doped with a second impurity of a second concentration, the second conductive pattern being disposed on the first conductive pattern. The first concentration may be higher than the second concentration.

公开(公告)号：US09129950B2

公开(公告)日：2015-09-08

申请号：US14568737

申请日：2014-12-12

Applicant: Jeeyong Kim ,  Woonkyung Lee ,  Sunggil Kim ,  Jin-Kyu Kang ,  Jung-Hwan Lee ,  Bonyoung Koo ,  Kihyun Hwang ,  Byoungsun Ju ,  Jintae Noh

Inventor： Jeeyong Kim ,  Woonkyung Lee ,  Sunggil Kim ,  Jin-Kyu Kang ,  Jung-Hwan Lee ,  Bonyoung Koo ,  Kihyun Hwang ,  Byoungsun Ju ,  Jintae Noh

IPC: H01L29/49 ,  H01L21/28 ,  H01L23/48 ,  H01L29/788 ,  H01L29/792 ,  H01L21/768 ,  H01L27/115

CPC classification number: H01L27/11526 ,  H01L21/28 ,  H01L21/76841 ,  H01L23/48 ,  H01L23/535 ,  H01L27/11521 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/4958 ,  H01L29/78 ,  H01L29/788 ,  H01L29/7883 ,  H01L29/792 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Provided are a semiconductor device and a method of manufacturing the semiconductor device. The semiconductor device includes a charge storage pattern formed on a substrate; a dielectric pattern formed on the charge storage pattern; a first conductive pattern including silicon doped with a first impurity of a first concentration, the first conductive pattern being disposed on the dielectric pattern; and a second conductive pattern including metal silicide doped with a second impurity of a second concentration, the second conductive pattern being disposed on the first conductive pattern. The first concentration may be higher than the second concentration.

Abstract translation: 提供半导体器件和制造半导体器件的方法。 半导体器件包括形成在衬底上的电荷存储图案; 形成在电荷存储图案上的电介质图案; 第一导电图案，包括掺杂有第一浓度的第一杂质的硅，所述第一导电图案设置在所述电介质图案上; 以及第二导电图案，其包括掺杂有第二浓度的第二杂质的金属硅化物，所述第二导电图案设置在所述第一导电图案上。 第一浓度可能高于第二浓度。