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    Vertical-type semiconductor device and method of manufacturing the same
    2.
    发明授权
    Vertical-type semiconductor device and method of manufacturing the same 有权
    立式半导体器件及其制造方法

    公开(公告)号：US08476713B2

    公开(公告)日：2013-07-02

    申请号：US12588270

    申请日：2009-10-09

    申请人： Seung-Jun Lee ,  Woonkyung Lee

    发明人： Seung-Jun Lee ,  Woonkyung Lee

    IPC分类号： H01L21/70 ,  H01L21/336

    CPC分类号： H01L27/11551 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11578 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7881 ,  H01L29/792 ,  H01L29/7926

    摘要： A vertical-type semiconductor device includes a semiconductor substrate having a cell region and a peripheral circuit region, a wordline structure on the cell region of the semiconductor substrate, the wordline structure including a plurality of wordlines stacked on top of each other, a semiconductor structure through the wordline structure, a gate dielectric between the wordline structure and the semiconductor structure, and a dummy wordline structure on the peripheral circuit region, the dummy wordline structure having a vertical structure and including same components as the wordline structure.

    摘要翻译： 垂直型半导体器件包括具有单元区域和外围电路区域的半导体衬底，半导体衬底的单元区域上的字线结构，该字线结构包括堆叠在彼此顶部的多个字线，半导体结构 通过字线结构，字线结构和半导体结构之间的栅极电介质和外围电路区域上的伪字线结构，虚拟字线结构具有垂直结构并且包括与字线结构相同的部件。

    THREE DIMENSIONAL SEMICONDUCTOR MEMORY DEVICES AND METHODS OF FABRICATING THE SAME
    3.
    发明申请
    THREE DIMENSIONAL SEMICONDUCTOR MEMORY DEVICES AND METHODS OF FABRICATING THE SAME 有权
    三维半导体存储器件及其制造方法

    公开(公告)号：US20120098049A1

    公开(公告)日：2012-04-26

    申请号：US13276682

    申请日：2011-10-19

    申请人： Hui-Chang MOON ,  Sung-Min Hwang ,  Woonkyung Lee

    发明人： Hui-Chang MOON ,  Sung-Min Hwang ,  Woonkyung Lee

    IPC分类号： H01L29/792

    CPC分类号： H01L27/11582 ,  H01L27/11556 ,  H01L29/7926

    摘要： A three dimensional semiconductor memory device has a stacked structure including cell gates stacked therein that are insulated from each other and first string selection gates laterally separated from each other, vertical active patterns extending through the first string selection gates, multi-layered dielectric layers between sidewalls of the vertical active patterns and the cell gates and between the sidewalls of the vertical active patterns and the first string selection gates, and at least one first supplement conductive pattern. The first string selection gates are disposed over an uppermost cell gate of the cell gates. Each vertical active pattern extends through each of the cell gates stacked under the first string selection gates. The first supplement conductive pattern is in contact with a sidewall of one of the first string selection gates.

    摘要翻译： 三维半导体存储器件具有层叠结构，其包括彼此绝缘的单元栅极和彼此横向分离的第一串选择栅极，延伸穿过第一串选择栅极的垂直有源图案，侧壁之间的多层电介质层 垂直有源图案和单元栅极之间以及垂直有源图案和第一串选择栅极的侧壁之间以及至少一个第一补充导电图案。 第一串选择栅极设置在单元栅极的最上面的单元栅极上。 每个垂直有源图案延伸穿过堆叠在第一串选择门下的每个单元门。 第一补充导电图案与第一串选择门之一的侧壁接触。

    THREE-DIMENSIONAL SEMICONDUCTOR DEVICE
    8.
    发明申请
    THREE-DIMENSIONAL SEMICONDUCTOR DEVICE 有权
    三维半导体器件

    公开(公告)号：US20140183756A1

    公开(公告)日：2014-07-03

    申请号：US14142158

    申请日：2013-12-27

    申请人： Sung-Min HWANG ,  Hansoo KIM ,  Woonkyung LEE ,  Wonseok CHO

    发明人： Sung-Min HWANG ,  Hansoo KIM ,  Woonkyung LEE ,  Wonseok CHO

    IPC分类号： H01L23/498

    CPC分类号： G11C16/0483 ,  H01L27/11556 ,  H01L27/11582 ,  H01L29/7889 ,  H01L29/7926 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A three-dimensional semiconductor device includes a substrate having a cell array region between first and second contact regions. A first stack includes a plurality of first electrodes vertically provided on the substrate, and a second stack includes a plurality of second electrodes vertically provided on the first stack. The second stack is arranged to expose end portions of the first electrodes on the first contact region and overlap end portions of the first electrodes on the second contact region.

    摘要翻译： 三维半导体器件包括在第一和第二接触区域之间具有单元阵列区域的衬底。 第一堆叠包括垂直设置在基板上的多个第一电极，第二堆叠包括垂直设置在第一堆叠上的多个第二电极。 第二堆叠被布置成暴露第一接触区域上的第一电极的端部并且在第二接触区域上重叠第一电极的端部。

    Three dimensional semiconductor memory devices and methods of fabricating the same
    9.
    发明授权
    Three dimensional semiconductor memory devices and methods of fabricating the same 有权
    三维半导体存储器件及其制造方法

    公开(公告)号：US08729622B2

    公开(公告)日：2014-05-20

    申请号：US13276682

    申请日：2011-10-19

    申请人： Hui-Chang Moon ,  Sung-Min Hwang ,  Woonkyung Lee

    发明人： Hui-Chang Moon ,  Sung-Min Hwang ,  Woonkyung Lee

    IPC分类号： H01L29/792

    CPC分类号： H01L27/11582 ,  H01L27/11556 ,  H01L29/7926

    摘要： A three dimensional semiconductor memory device has a stacked structure including cell gates stacked therein that are insulated from each other and first string selection gates laterally separated from each other, vertical active patterns extending through the first string selection gates, multi-layered dielectric layers between sidewalls of the vertical active patterns and the cell gates and between the sidewalls of the vertical active patterns and the first string selection gates, and at least one first supplement conductive pattern. The first string selection gates are disposed over an uppermost cell gate of the cell gates. Each vertical active pattern extends through each of the cell gates stacked under the first string selection gates. The first supplement conductive pattern is in contact with a sidewall of one of the first string selection gates.

    摘要翻译： 三维半导体存储器件具有层叠结构，其包括彼此绝缘的单元栅极和彼此横向分离的第一串选择栅极，延伸穿过第一串选择栅极的垂直有源图案，侧壁之间的多层电介质层 垂直有源图案和单元栅极之间以及垂直有源图案和第一串选择栅极的侧壁之间以及至少一个第一补充导电图案。 第一串选择栅极设置在单元栅极的最上面的单元栅极上。 每个垂直有源图案延伸穿过堆叠在第一串选择门下的每个单元门。 第一补充导电图案与第一串选择门之一的侧壁接触。

    Vertical type semiconductor device
    10.
    发明授权
    Vertical type semiconductor device 有权
    垂直型半导体器件

    公开(公告)号：US08513731B2

    公开(公告)日：2013-08-20

    申请号：US12588491

    申请日：2009-10-16

    申请人： Seung-Jun Lee ,  Woonkyung Lee

    发明人： Seung-Jun Lee ,  Woonkyung Lee

    IPC分类号： H01L29/66

    CPC分类号： H01L27/11578 ,  H01L27/0688 ,  H01L27/11582

    摘要： A vertical type semiconductor device including a first vertical semiconductor device on a semiconductor substrate, a second vertical semiconductor device on the first vertical semiconductor device, and an interconnection between the first and second vertical semiconductor devices.

    摘要翻译： 一种垂直型半导体器件，包括半导体衬底上的第一垂直半导体器件，第一垂直半导体器件上的第二垂直半导体器件以及第一和第二垂直半导体器件之间的互连。