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    Nonvolatile memory device and method of forming the same
    1.
    发明授权
    Nonvolatile memory device and method of forming the same 失效
    非易失存储器件及其形成方法

    公开(公告)号：US08278698B2

    公开(公告)日：2012-10-02

    申请号：US12703066

    申请日：2010-02-09

    Applicant: Toshiro Nakanishi ,  Chanjin Park ,  Siyoung Choi ,  Bonyoung Koo

    Inventor： Toshiro Nakanishi ,  Chanjin Park ,  Siyoung Choi ,  Bonyoung Koo

    IPC: H01L29/792

    CPC classification number: H01L27/11568 ,  H01L21/28282 ,  H01L27/11565

    Abstract: A nonvolatile memory device includes a device isolation pattern, a charge trap layer, and a plurality of word lines. The device isolation pattern defines an active region in a semiconductor substrate and extends in a first direction. The charge trap layer covers the active region and the device isolation pattern. The word lines on the charge trap layer cross the active region and extend in a second direction. The charge trap layer disposed in a first region where the word line and the active region cross each other has a different nitrogen content ratio from the charge trap layer disposed in a second region surrounding the first region.

    Abstract translation: 非易失性存储器件包括器件隔离图案，电荷陷阱层和多个字线。 器件隔离图案限定半导体衬底中的有源区并沿第一方向延伸。 电荷陷阱层覆盖有源区和器件隔离图案。 电荷陷阱层上的字线穿过有源区并沿第二方向延伸。 设置在字线和有源区彼此交叉的第一区域中的电荷陷阱层与设置在围绕第一区域的第二区域中的电荷陷阱层具有不同的氮含量比。

    SEMICONDUCTOR DEVICE INCLUDING FIELD EFFECT TRANSISTORS
    3.
    发明申请
    SEMICONDUCTOR DEVICE INCLUDING FIELD EFFECT TRANSISTORS 有权
    包括场效应晶体管的半导体器件

    公开(公告)号：US20160336450A1

    公开(公告)日：2016-11-17

    申请号：US15093892

    申请日：2016-04-08

    Applicant: Yong-Suk TAK ,  Jongryeol YOO ,  Hyun Jung LEE ,  Miseon PARK ,  Bonyoung KOO ,  Sunjung KIM

    Inventor： Yong-Suk TAK ,  Jongryeol YOO ,  Hyun Jung LEE ,  Miseon PARK ,  Bonyoung KOO ,  Sunjung KIM

    IPC: H01L29/78 ,  H01L29/08

    CPC classification number: H01L29/7851 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/7848 ,  H01L29/7849

    Abstract: A semiconductor device includes a fin structure on a substrate and extending in a first direction, a gate electrode crossing over the fin structure, source/drain regions on the fin structure at opposite sides of the gate electrode, and a barrier layer between the fin structure and each of the source/drain regions. The fin structure includes a material having a lattice constant different from that of the substrate, the fin structure, the source/drain regions, and the barrier layer include germanium, and a germanium concentration in the barrier layer is greater than that in the fin structure and less than a maximum germanium concentration in each of the source/drain regions.

    Abstract translation: 半导体器件包括在衬底上并沿第一方向延伸的翅片结构，在翅片结构上交叉的栅电极，在栅电极的相对侧的翅片结构上的源/漏区和鳍结构之间的阻挡层 和源极/漏极区域中的每一个。 翅片结构包括具有与衬底的晶格常数不同的晶格常数的材料，鳍结构，源极/漏极区和阻挡层包括锗，并且阻挡层中的锗浓度大于鳍结构中的锗浓度 并且在每个源极/漏极区域中小于最大锗浓度。

    Nonvolatile Memory Device and Method of Forming the Same
    6.
    发明申请
    Nonvolatile Memory Device and Method of Forming the Same 失效
    非易失性存储器件及其形成方法

    公开(公告)号：US20100213536A1

    公开(公告)日：2010-08-26

    申请号：US12703066

    申请日：2010-02-09

    Applicant: Toshiro Nakanishi ,  Chanjin Park ,  Siyoung Choi ,  Bonyoung Koo

    Inventor： Toshiro Nakanishi ,  Chanjin Park ,  Siyoung Choi ,  Bonyoung Koo

    IPC: H01L27/115

    CPC classification number: H01L27/11568 ,  H01L21/28282 ,  H01L27/11565

    Abstract: A nonvolatile memory device includes a device isolation pattern, a charge trap layer, and a plurality of word lines. The device isolation pattern defines an active region in a semiconductor substrate and extends in a first direction. The charge trap layer covers the active region and the device isolation pattern. The word lines on the charge trap layer cross the active region and extend in a second direction. The charge trap layer disposed in a first region where the word line and the active region cross each other has a different nitrogen content ratio from the charge trap layer disposed in a second region surrounding the first region.

    Abstract translation: 非易失性存储器件包括器件隔离图案，电荷陷阱层和多个字线。 器件隔离图案限定半导体衬底中的有源区并沿第一方向延伸。 电荷陷阱层覆盖有源区和器件隔离图案。 电荷陷阱层上的字线穿过有源区并沿第二方向延伸。 设置在字线和有源区彼此交叉的第一区域中的电荷陷阱层与设置在围绕第一区域的第二区域中的电荷陷阱层具有不同的氮含量比。

    SEMICONDUCTOR DEVICE HAVING FIN ACTIVE REGIONS AND METHOD OF FABRICATING THE SAME
    7.
    发明申请
    SEMICONDUCTOR DEVICE HAVING FIN ACTIVE REGIONS AND METHOD OF FABRICATING THE SAME 有权
    具有精细活性区域的半导体器件及其制造方法

    公开(公告)号：US20160315081A1

    公开(公告)日：2016-10-27

    申请号：US15013969

    申请日：2016-02-02

    Applicant: Miseon PARK ,  Jongryeol YOO ,  Hyunjung LEE ,  Yong-Suk TAK ,  Bonyoung KOO ,  Sunjung KIM

    Inventor： Miseon PARK ,  Jongryeol YOO ,  Hyunjung LEE ,  Yong-Suk TAK ,  Bonyoung KOO ,  Sunjung KIM

    IPC: H01L27/088 ,  H01L29/417 ,  H01L29/08 ,  H01L29/06 ,  H01L29/161

    CPC classification number: H01L27/0886 ,  H01L21/823425 ,  H01L21/823431 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/41791

    Abstract: A semiconductor device may include fin active regions extending parallel to each other on a substrate, an isolation region between the fin active regions, gate patterns intersecting the fin active regions and extending parallel to each other, source/drain areas on the fin active regions between the gate patterns and fin active region spacers contacting side surfaces of the fin active regions and formed over a surface of the isolation region between the fin active regions. Uppermost levels of the fin active region spacers may be higher than interfaces between the fin active regions and the source/drain areas. The upper surface of the isolation region may be lower than bottom surfaces of the source/drain areas.

    Abstract translation: 半导体器件可以包括在衬底上彼此平行延伸的翅片有源区域，翅片有源区域之间的隔离区域，与翅片有源区域相交并且彼此平行延伸的栅极图案，翅片有源区域之间的源极/漏极区域在 所述栅极图案和鳍状有源区间隔物接触所述翅片有源区域的侧表面并形成在所述鳍片活动区域之间的所述隔离区域的表面上。 翅片有源区间隔物的最上层可以高于翅片有源区和源极/漏极区之间的界面。 隔离区域的上表面可以低于源/漏区域的底表面。

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