公开(公告)号：US08476692B2

公开(公告)日：2013-07-02

申请号：US13037502

申请日：2011-03-01

申请人： Jeeyong Kim ,  WoonKyung Lee ,  Sunggil Kim ,  Jin-Kyu Kang ,  Jung-Hwan Lee ,  Bonyoung Koo ,  Kihyun Hwang ,  Byoungsun Ju ,  Jintae Noh

发明人： Jeeyong Kim ,  WoonKyung Lee ,  Sunggil Kim ,  Jin-Kyu Kang ,  Jung-Hwan Lee ,  Bonyoung Koo ,  Kihyun Hwang ,  Byoungsun Ju ,  Jintae Noh

IPC分类号： H01L29/778

CPC分类号： H01L27/11526 ,  H01L21/28 ,  H01L21/76841 ,  H01L23/48 ,  H01L23/535 ,  H01L27/11521 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/4958 ,  H01L29/78 ,  H01L29/788 ,  H01L29/7883 ,  H01L29/792 ,  H01L2924/0002 ,  H01L2924/00

摘要： Provided are a semiconductor device and a method of manufacturing the semiconductor device. The semiconductor device includes a charge storage pattern formed on a substrate; a dielectric pattern formed on the charge storage pattern; a first conductive pattern including silicon doped with a first impurity of a first concentration, the first conductive pattern being disposed on the dielectric pattern; and a second conductive pattern including metal silicide doped with a second impurity of a second concentration, the second conductive pattern being disposed on the first conductive pattern. The first concentration may be higher than the second concentration.

摘要翻译： 提供半导体器件和制造半导体器件的方法。 半导体器件包括形成在衬底上的电荷存储图案; 形成在电荷存储图案上的电介质图案; 第一导电图案，包括掺杂有第一浓度的第一杂质的硅，所述第一导电图案设置在所述电介质图案上; 以及第二导电图案，其包括掺杂有第二浓度的第二杂质的金属硅化物，所述第二导电图案设置在所述第一导电图案上。 第一浓度可能高于第二浓度。

公开(公告)号：US20150145018A1

公开(公告)日：2015-05-28

申请号：US14568737

申请日：2014-12-12

申请人： Jeeyong Kim ,  Woonkyung Lee ,  Sunggil Kim ,  Jin-Kyu Kang ,  Jung-Hwan Lee ,  Bonyoung Koo ,  Kihyun Hwang ,  Byoungsun Ju ,  Jintae Noh

发明人： Jeeyong Kim ,  Woonkyung Lee ,  Sunggil Kim ,  Jin-Kyu Kang ,  Jung-Hwan Lee ,  Bonyoung Koo ,  Kihyun Hwang ,  Byoungsun Ju ,  Jintae Noh

IPC分类号： H01L29/49 ,  H01L27/115 ,  H01L29/788

CPC分类号： H01L27/11526 ,  H01L21/28 ,  H01L21/76841 ,  H01L23/48 ,  H01L23/535 ,  H01L27/11521 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/4958 ,  H01L29/78 ,  H01L29/788 ,  H01L29/7883 ,  H01L29/792 ,  H01L2924/0002 ,  H01L2924/00

摘要： Provided are a semiconductor device and a method of manufacturing the semiconductor device. The semiconductor device includes a charge storage pattern formed on a substrate; a dielectric pattern formed on the charge storage pattern; a first conductive pattern including silicon doped with a first impurity of a first concentration, the first conductive pattern being disposed on the dielectric pattern; and a second conductive pattern including metal silicide doped with a second impurity of a second concentration, the second conductive pattern being disposed on the first conductive pattern. The first concentration may be higher than the second concentration.

摘要翻译： 提供半导体器件和制造半导体器件的方法。 半导体器件包括形成在衬底上的电荷存储图案; 形成在电荷存储图案上的电介质图案; 第一导电图案，包括掺杂有第一浓度的第一杂质的硅，所述第一导电图案设置在所述电介质图案上; 以及第二导电图案，其包括掺杂有第二浓度的第二杂质的金属硅化物，所述第二导电图案设置在所述第一导电图案上。 第一浓度可能高于第二浓度。

公开(公告)号：US20110215392A1

公开(公告)日：2011-09-08

申请号：US13037502

申请日：2011-03-01

申请人： Jeeyong Kim ,  WoonKyung Lee ,  Sunggil Kim ,  Jin-Kyu Kang ,  Jung-Hwan Lee ,  Bonyoung Koo ,  Kihyun Hwang ,  Byoungsun Ju ,  Jintae Noh

发明人： Jeeyong Kim ,  WoonKyung Lee ,  Sunggil Kim ,  Jin-Kyu Kang ,  Jung-Hwan Lee ,  Bonyoung Koo ,  Kihyun Hwang ,  Byoungsun Ju ,  Jintae Noh

IPC分类号： H01L29/788 ,  H01L21/28 ,  H01L23/48 ,  H01L29/792

CPC分类号： H01L27/11526 ,  H01L21/28 ,  H01L21/76841 ,  H01L23/48 ,  H01L23/535 ,  H01L27/11521 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/4958 ,  H01L29/78 ,  H01L29/788 ,  H01L29/7883 ,  H01L29/792 ,  H01L2924/0002 ,  H01L2924/00

摘要： Provided are a semiconductor device and a method of manufacturing the semiconductor device. The semiconductor device includes a charge storage pattern formed on a substrate; a dielectric pattern formed on the charge storage pattern; a first conductive pattern including silicon doped with a first impurity of a first concentration, the first conductive pattern being disposed on the dielectric pattern; and a second conductive pattern including metal silicide doped with a second impurity of a second concentration, the second conductive pattern being disposed on the first conductive pattern. The first concentration may be higher than the second concentration.

摘要翻译： 提供半导体器件和制造半导体器件的方法。 半导体器件包括形成在衬底上的电荷存储图案; 形成在电荷存储图案上的电介质图案; 第一导电图案，包括掺杂有第一浓度的第一杂质的硅，所述第一导电图案设置在所述电介质图案上; 以及第二导电图案，其包括掺杂有第二浓度的第二杂质的金属硅化物，所述第二导电图案设置在所述第一导电图案上。 第一浓度可能高于第二浓度。

公开(公告)号：US09443863B2

公开(公告)日：2016-09-13

申请号：US14819841

申请日：2015-08-06

申请人： Jeeyong Kim ,  Woonkyung Lee ,  Sunggil Kim ,  Jin-Kyu Kang ,  Jung-Hwan Lee ,  Bonyoung Koo ,  Kihyun Hwang ,  Byoungsun Ju ,  Jintae Noh

发明人： Jeeyong Kim ,  Woonkyung Lee ,  Sunggil Kim ,  Jin-Kyu Kang ,  Jung-Hwan Lee ,  Bonyoung Koo ,  Kihyun Hwang ,  Byoungsun Ju ,  Jintae Noh

IPC分类号： H01L29/49 ,  H01L27/115 ,  H01L23/535 ,  H01L29/78 ,  H01L21/28 ,  H01L23/48 ,  H01L29/788 ,  H01L29/792 ,  H01L21/768

CPC分类号： H01L27/11526 ,  H01L21/28 ,  H01L21/76841 ,  H01L23/48 ,  H01L23/535 ,  H01L27/11521 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/4958 ,  H01L29/78 ,  H01L29/788 ,  H01L29/7883 ,  H01L29/792 ,  H01L2924/0002 ,  H01L2924/00

摘要： Provided are a semiconductor device and a method of manufacturing the semiconductor device. The semiconductor device includes a charge storage pattern formed on a substrate; a dielectric pattern formed on the charge storage pattern; a first conductive pattern including silicon doped with a first impurity of a first concentration, the first conductive pattern being disposed on the dielectric pattern; and a second conductive pattern including metal silicide doped with a second impurity of a second concentration, the second conductive pattern being disposed on the first conductive pattern. The first concentration may be higher than the second concentration.

公开(公告)号：US09129950B2

公开(公告)日：2015-09-08

申请号：US14568737

申请日：2014-12-12

申请人： Jeeyong Kim ,  Woonkyung Lee ,  Sunggil Kim ,  Jin-Kyu Kang ,  Jung-Hwan Lee ,  Bonyoung Koo ,  Kihyun Hwang ,  Byoungsun Ju ,  Jintae Noh

发明人： Jeeyong Kim ,  Woonkyung Lee ,  Sunggil Kim ,  Jin-Kyu Kang ,  Jung-Hwan Lee ,  Bonyoung Koo ,  Kihyun Hwang ,  Byoungsun Ju ,  Jintae Noh

IPC分类号： H01L29/49 ,  H01L21/28 ,  H01L23/48 ,  H01L29/788 ,  H01L29/792 ,  H01L21/768 ,  H01L27/115

CPC分类号： H01L27/11526 ,  H01L21/28 ,  H01L21/76841 ,  H01L23/48 ,  H01L23/535 ,  H01L27/11521 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/4958 ,  H01L29/78 ,  H01L29/788 ,  H01L29/7883 ,  H01L29/792 ,  H01L2924/0002 ,  H01L2924/00

摘要： Provided are a semiconductor device and a method of manufacturing the semiconductor device. The semiconductor device includes a charge storage pattern formed on a substrate; a dielectric pattern formed on the charge storage pattern; a first conductive pattern including silicon doped with a first impurity of a first concentration, the first conductive pattern being disposed on the dielectric pattern; and a second conductive pattern including metal silicide doped with a second impurity of a second concentration, the second conductive pattern being disposed on the first conductive pattern. The first concentration may be higher than the second concentration.

摘要翻译： 提供半导体器件和制造半导体器件的方法。 半导体器件包括形成在衬底上的电荷存储图案; 形成在电荷存储图案上的电介质图案; 第一导电图案，包括掺杂有第一浓度的第一杂质的硅，所述第一导电图案设置在所述电介质图案上; 以及第二导电图案，其包括掺杂有第二浓度的第二杂质的金属硅化物，所述第二导电图案设置在所述第一导电图案上。 第一浓度可能高于第二浓度。

公开(公告)号：US09666525B2

公开(公告)日：2017-05-30

申请号：US15201994

申请日：2016-07-05

申请人： Jeeyong Kim ,  Daeseok Byeon ,  Jung-Hwan Lee ,  Sanghoon Ahn

发明人： Jeeyong Kim ,  Daeseok Byeon ,  Jung-Hwan Lee ,  Sanghoon Ahn

IPC分类号： H01L29/792 ,  H01L23/522 ,  H01L27/1157 ,  H01L27/11582 ,  H01L23/528 ,  H01L27/11573

CPC分类号： H01L23/5226 ,  H01L21/7682 ,  H01L23/528 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582 ,  H01L2221/1047

摘要： Three-dimensional (3D) semiconductor memory devices capable of improving reliability may be provided. For example, a three dimensional (3D) memory device, in which a plurality of memory cell strings are vertically arranged, may include a substrate, a stack structure of alternating a plurality of interlayer dielectric (ILD) layers and a plurality of gate electrodes, at least one of the ILD layers including pores, a vertical structure penetrating the stack structure and electrically connected to the substrate, and a data storage layer between the stack structure and the vertical structure.

公开(公告)号：US20160268302A1

公开(公告)日：2016-09-15

申请号：US14995845

申请日：2016-01-14

申请人： Jung-Hwan Lee ,  Jee-Yong Kim ,  Dae-Seok Byeon

发明人： Jung-Hwan Lee ,  Jee-Yong Kim ,  Dae-Seok Byeon

IPC分类号： H01L27/115

CPC分类号： H01L27/11582 ,  H01L21/28282 ,  H01L27/11565 ,  H01L27/1157 ,  H01L29/42352 ,  H01L29/66833

摘要： Semiconductor devices are provided. A semiconductor device includes a stack of alternating insulation layers and gate electrodes. The semiconductor device includes a channel material in a channel recess in the stack. The semiconductor device includes a charge storage structure on the channel material, in the channel recess. Moreover, the semiconductor device includes a gate insulation layer on the channel material. The gate insulation layer undercuts a portion of the channel material. Related methods of forming semiconductor devices are also provided.

摘要翻译： 提供半导体器件。 半导体器件包括交替绝缘层和栅电极的叠层。 半导体器件包括在堆叠中的通道凹槽中的沟道材料。 半导体器件在通道凹槽中包括在沟道材料上的电荷存储结构。 此外，半导体器件在沟道材料上包括栅极绝缘层。 栅极绝缘层将沟道材料的一部分切下。 还提供了形成半导体器件的相关方法。

公开(公告)号：US09281202B2

公开(公告)日：2016-03-08

申请号：US12604757

申请日：2009-10-23

申请人： Tae-Ho Choi ,  Jung-Hwan Lee ,  Heung-Gee Hong ,  Jeong-Ho Cho ,  Min-Wan Choo ,  Il-Seok Han

发明人： Tae-Ho Choi ,  Jung-Hwan Lee ,  Heung-Gee Hong ,  Jeong-Ho Cho ,  Min-Wan Choo ,  Il-Seok Han

IPC分类号： H01L29/423 ,  H01L21/28 ,  H01L29/51 ,  H01L29/66 ,  H01L29/788

CPC分类号： H01L21/28273 ,  H01L29/42324 ,  H01L29/512 ,  H01L29/66825 ,  H01L29/7881

摘要： A nonvolatile memory cell and a method for fabricating the same can secure stable operational reliability as well as reducing a cell size. The nonvolatile memory cell includes a drain region formed in a substrate, a source region formed in the substrate to be separated from the drain region, a floating gate formed over the substrate between the drain region and the source region, a halo region formed in the substrate in a direction that the drain region is formed, a dielectric layer formed on sidewalls of the floating gate, and a control gate formed over the dielectric layer to overlap with at least one sidewall of the floating gate.

摘要翻译： 非易失性存储单元及其制造方法可以确保稳定的操作可靠性以及减小单元尺寸。 非易失性存储单元包括形成在衬底中的漏极区，形成在衬底中的与漏极区分离的源极区，在漏极区和源极区之间形成在衬底上的浮置栅， 在形成漏极区域的方向上形成衬底，形成在浮置栅极的侧壁上的电介质层以及形成在电介质层上以与浮动栅极的至少一个侧壁重叠的控制栅极。

公开(公告)号：US20110262922A1

公开(公告)日：2011-10-27

申请号：US13092209

申请日：2011-04-22

申请人： Young-Chan CHAE ,  Youn-Dong Kim ,  Jung-Hwan Lee ,  Ki-Seok Kim ,  Dong-II Han ,  Bum-Su Park ,  Seung-Jin Lee ,  Jong-Hun Im ,  Jong-In Kim ,  Sung-Ho Ryu ,  Sung-Key Jang

发明人： Young-Chan CHAE ,  Youn-Dong Kim ,  Jung-Hwan Lee ,  Ki-Seok Kim ,  Dong-II Han ,  Bum-Su Park ,  Seung-Jin Lee ,  Jong-Hun Im ,  Jong-In Kim ,  Sung-Ho Ryu ,  Sung-Key Jang

IPC分类号： G01N33/566 ,  G01N21/64 ,  G01N33/74 ,  G01N33/92 ,  G01N33/82 ,  G01N21/75 ,  C12Q1/68

CPC分类号： G01N33/5308

摘要： The present invention provides methods for identifying the plurality of aptamers that bind to different sites of a target molecule and methods for using the same, for example, in sandwich assays. In particular, the plurality of aptamers binding to different sites of the target molecules is identified from a library of aptamers identified from the same SELEX process.

摘要翻译： 本发明提供用于鉴定结合靶分子的不同位点的多个适体的方法以及使用其的方法，例如在夹心测定中。 特别地，从相同SELEX过程鉴定的适配体文库中鉴定结合靶分子不同位点的多个适体。

公开(公告)号：US20100123656A1

公开(公告)日：2010-05-20

申请号：US12604820

申请日：2009-10-23

申请人： KYU-CHEOL PARK ,  Jung-Hwan Lee ,  Won-Jang Park ,  Byung-Chun Sakong ,  Sang-Bum Kim ,  Woo-Hee Yang

发明人： KYU-CHEOL PARK ,  Jung-Hwan Lee ,  Won-Jang Park ,  Byung-Chun Sakong ,  Sang-Bum Kim ,  Woo-Hee Yang

IPC分类号： G09G5/00

CPC分类号： G06F3/0346

摘要： Provided is an input device for operating in a three-dimensional space and inputting user instructions. The input device includes a first operation unit that calculates a first rotation angle in a coordinate system independent of the attitude of the device based on the output value of a first sensor, a second operation unit that calculates a second rotation angle in the coordinate system based on the output value of a second sensor, an attitude angle measuring unit that calculates the attitude angle of the input device by combining the first rotation angle and the second rotation angle, and an intensity calculation unit that calculates force intensity in the coordinate system using acceleration of the input device and the attitude angle of the input device obtained in the attitude measuring unit.

摘要翻译： 提供了一种用于在三维空间中操作并输入用户指令的输入装置。 输入装置包括第一操作单元，其基于第一传感器的输出值，计算独立于设备姿态的坐标系中的第一旋转角度，第二操作单元，其以坐标系为基础计算第二旋转角度 在第二传感器的输出值上，姿态角测量单元，其通过组合第一旋转角度和第二旋转角度来计算输入装置的姿态角度;以及强度计算单元，其使用加速度来计算坐标系中的力强度 和姿态测量单元中获得的输入装置的姿态角。