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公开(公告)号：US07265006B2
公开(公告)日：2007-09-04
申请号：US11176538
申请日：2005-07-07
IPC分类号： H01L21/337
CPC分类号： H01L27/14643 , H01L27/14632 , H01L27/14636 , H01L27/14687 , H01L27/14689
摘要： A method of fabricating heterojunction devices, in which heterojunction devices are epitaxially formed on active area regions surrounded by field oxide regions and containing embedded semiconductor wells. The epitaxial growth of the heterojunction device layers may be selective or not and the epitaxial layer may be formed so as to contact individually each one of a plurality of heterojunction devices or contact a plurality of heterojunction devices in parallel. This method can be used to fabricate three-terminal devices and vertically stacked devices.
摘要翻译： 一种制造异质结器件的方法，其中异质结器件外延形成在由场氧化物区域包围并包含嵌入式半导体阱的有源区域区域上。 异质结器件层的外延生长可以是选择性的或不是可选的，并且外延层可以形成为单独地接触多个异质结装置中的每一个或者并联接触多个异质结装置。 该方法可用于制造三端子器件和垂直堆叠器件。
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公开(公告)号：US20100270459A1
公开(公告)日：2010-10-28
申请号：US12765936
申请日：2010-04-23
IPC分类号： H01L27/148
CPC分类号： H01L27/14609 , H01L27/14837 , H01L27/14843 , H01L27/1485 , H01L27/14868 , H01L31/02021 , H01L31/04
摘要： A photo-current mode of operation is disclosed for Full Frame CCDs, and Frame-Transfer CCDs, that is suitable for electrical power generation, when not in operation for image sensing, and for Interline-Transfer CCDs, that is suitable for image sensing, and also suitable electrical power generation, when not in operation for image sensing. Further, CMOS Image Sensors (CIS), including 1T Passive Pixels, or 1T Avalanche Photo-Diode Pixels, in which all pass transistors in the matrix are turned ON simultaneously thereby allowing the photo-current produced by each photo-diode in each pixel to flow towards the periphery where suitable circuitry will handle the photo-current for electrical power generation and/or storage. Also, CMOS Image Sensors (CIS), including any Active Pixel Sensor (APS) design, such as the 3T, or 3T Log, or 4T, or 5T, wherein each column-parallel VDD line connecting the Reset Transistors, or the Log Transistors, in a single column of pixels, to column-parallel circuitry at the edge of the pixel matrix, is connected through multiple pass transistors, to different column-parallel blocks of circuitry that are selected alternatively, and that include (1) a VDD voltage source for standard image sensing operation, (2) a block of circuitry suitable to handle photo-current signals for image sensing purposes, and (3) a block of circuitry that is suitable to handle photo-current for electrical power generation and/or storage purposes.
摘要翻译： 对于适用于图像感测不适用于发电的全帧CCD和帧转移CCD以及适用于图像感测的线间传输CCD，公开了光电流操作模式， 并且当不用于图像感测时也适合发电。 此外，包括1T无源像素或1T雪崩光电二极管像素的CMOS图像传感器（CIS），其中矩阵中的全部通过晶体管同时导通，从而允许每个像素中的每个光电二极管产生的光电流 流向外围，其中合适的电路将处理用于发电和/或存储的光电流。 此外，CMOS图像传感器（CIS）包括任何有源像素传感器（APS）设计，例如3T或3T Log，或4T或5T，其中连接复位晶体管的每个并联的VDD线或对数晶体管 在单个像素列中，在像素矩阵的边缘处的列并联电路通过多通道晶体管连接到可选择的不同列并联的电路块，并且包括（1）VDD电压 用于标准图像感测操作的源，（2）适于处理用于图像感测目的的光电流信号的电路块，以及（3）适于处理用于发电和/或存储的光电流的电路块 目的
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公开(公告)号：US20100178018A1
公开(公告)日：2010-07-15
申请号：US12676985
申请日：2007-09-06
CPC分类号： G02B6/1225 , G02B6/08 , G02B6/12 , G02B6/4249 , G02B6/4298 , G02B6/43 , G02B2006/12166 , G02B2006/12176 , H01L27/14621 , H01L27/14629 , H01L27/14636 , H01L27/14685 , H01L31/0232
摘要： Photonic passive structure to couple and guide light between photonic active devices (101), such as photo-diodes, light emitting devices and light-valves, which may be arranged into 2D arrays, and the top of the metallization layer stack (110,111,112) interconnecting said devices, with said photonic passive structure comprising a hole (116) between the near surface of said photonic active Ndevices and the top of said metallization stack, said hole being filled with a dielectric (113) having embedded metal films (117) and in which the embedded metal thin films are connected to a planar perforated metal film (123,124) formed on top of the metallization stack.
摘要翻译： 可以布置成2D阵列的光子二极管，发光器件和光阀之间的光子有源器件（101）耦合和引导光的光子无源结构以及互连的金属化层堆叠（110,111,112）的顶部 所述器件具有所述光子被动结构，其包括在所述光子活性Ndevices的近表面和所述金属化堆叠的顶部之间的孔（116），所述孔填充有具有嵌入金属膜（117）的电介质（113） 其中嵌入的金属薄膜连接到形成在金属化叠层顶部上的平面穿孔金属膜（123,124）。
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公开(公告)号：US20060014334A1
公开(公告)日：2006-01-19
申请号：US11135996
申请日：2005-05-24
IPC分类号： H01L21/8249
CPC分类号： H01L21/84 , H01L21/8249
摘要： A method of fabricating heterojunction devices, in which heterojunction devices are epitaxially formed on active area regions surrounded by field oxide regions and containing embedded semiconductor wells. The epitaxial growth of the heterojunction device layers may be selective or not and the epitaxial layer may be formed so as to contact individually each one of a plurality of heterojunction devices or contact a plurality of heterojunction devices in parallel. This method can be used to fabricate three-terminal devices and vertically stacked devices.
摘要翻译： 一种制造异质结器件的方法，其中异质结器件外延形成在由场氧化物区域包围并包含嵌入式半导体阱的有源区域区域上。 异质结器件层的外延生长可以是选择性的或不是可选的，并且外延层可以形成为单独地接触多个异质结装置中的每一个或者并联接触多个异质结装置。 该方法可用于制造三端子器件和垂直堆叠器件。
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公开(公告)号：US20090173976A1
公开(公告)日：2009-07-09
申请号：US12403900
申请日：2009-03-13
IPC分类号： H01L33/00
CPC分类号： H01L27/14669 , H01L27/14609 , H01L31/035254 , H01L31/107
摘要： A method of fabricating multi-spectral photo-sensors including photo-diodes incorporating stacked epitaxial superlattices monolithically integrated with CMOS devices on a common semiconductor substrate.
摘要翻译： 一种制造多光谱光电传感器的方法，包括结合堆叠的外延超晶格的光电二极管，其在公共半导体衬底上与CMOS器件单片集成。
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公开(公告)号：US20080150782A1
公开(公告)日：2008-06-26
申请号：US12000049
申请日：2007-12-07
IPC分类号： H03M1/12
CPC分类号： H03M1/1014 , H03M1/125 , H04N5/3698 , H04N5/374 , H04N5/378
摘要： An analog-to-digital converter apparatus for analog source signals of one polarity, includes one comparator formed from transistors, a block of digitally addressable voltage sources to set a reference voltage of the comparator, an asynchronous n-bit digital counter, a block of digitally addressable voltage sources to set the potential to be applied to the signal source, a digital control unit, a block storing the calibration data for an input capacitor of the comparator, and a base-2 multiplier block, being interconnected by lines, including a line connecting the input analog signal to the drain of a pass transistor, a line connecting the block of voltage sources to be connected to the signal source, a line connecting the digital control unit to transistor gates, and a line carrying the signal Vref from the block of digitally addressed voltage sources to the comparator.
摘要翻译： 一种极性的模拟源信号的模拟 - 数字转换器装置包括由晶体管形成的一个比较器，用于设置比较器的参考电压的一组数字寻址电压源，异步n位数字计数器， 数字寻址电压源，用于设置施加到信号源的电位，数字控制单元，存储用于比较器的输入电容器的校准数据的块和通过线互连的基2乘法器块，包括 将输入模拟信号连接到传输晶体管的漏极，连接要连接到信号源的电压源块的线，将数字控制单元连接到晶体管栅极的线以及从该晶体管 数字寻址电压源的块到比较器。
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