公开(公告)号：US07566924B2

公开(公告)日：2009-07-28

申请号：US11249096

申请日：2005-10-11

Applicant: Chang-Huhn Lee ,  Mun-Mo Jeong ,  Wook-je Kim

Inventor： Chang-Huhn Lee ,  Mun-Mo Jeong ,  Wook-je Kim

IPC: H01L31/112

CPC classification number: H01L29/6656 ,  H01L21/823468 ,  Y10S257/90 ,  Y10S438/978

Abstract: Embodiments of the invention provide a semiconductor device and a fabrication method for a semiconductor device that includes the processes of forming multiple gates on a silicon substrate, forming a gate spacer having a positive slope at the gate spacer edge, depositing a polysilicon layer on the silicon substrate between the gates, etching a portion of the polysilicon layer to form an opening exposing a portion of the silicon substrate, and forming an inter-insulation layer to the exposed portion of the silicon substrate to fill the opening. Using an annealing process applied to a layer in the gate spacer, the etch selectivity can be selectively controlled and consequently, the degree of slope at the gate spacer edge is predetermined.

Abstract translation: 本发明的实施例提供一种用于半导体器件的半导体器件和制造方法，其包括在硅衬底上形成多个栅极的工艺，在栅极间隔物边缘处形成具有正斜率的栅极间隔物，在硅上沉积多晶硅层 蚀刻多晶硅层的一部分以形成露出硅衬底的一部分的开口，以及形成绝缘层到硅衬底的暴露部分以填充开口。 使用施加到栅极间隔物中的层的退火工艺，可以选择性地控制蚀刻选择性，因此预定栅极间隔物边缘处的斜率。

公开(公告)号：US20090246930A1

公开(公告)日：2009-10-01

申请号：US12469422

申请日：2009-05-20

Applicant: Seok-Woo HONG ,  Chang-Huhn LEE ,  Jae-Hun KIM

Inventor： Seok-Woo HONG ,  Chang-Huhn LEE ,  Jae-Hun KIM

IPC: H01L27/06 ,  H01L21/02

CPC classification number: H01L28/84 ,  H01L27/10852

Abstract: Disclosed is a metal capacitor including a lower electrode having hemispherical metal grains thereon. The metal capacitor includes a lower metal electrode containing Ti, hemispherical metal grains containing Pd and formed on the lower metal electrode containing Ti, a dielectric layer formed on the lower metal electrode containing Ti and the hemispherical metal grains containing Pd, and an upper metal electrode formed on the dielectric layer.

Abstract translation: 公开了一种金属电容器，其包括其上具有半球形金属颗粒的下电极。 金属电容器包括含有Ti的下部金属电极，形成在含有Ti的下部金属电极上形成的含有Pd的半球形金属颗粒，形成在含有Ti的下部金属电极上的介电层和包含Pd的半球状金属颗粒和上部金属电极 形成在电介质层上。

公开(公告)号：US20060027875A1

公开(公告)日：2006-02-09

申请号：US11249096

申请日：2005-10-11

Applicant: Chang-Huhn Lee ,  Mun-Mo Jeong ,  Wook-je Kim

Inventor： Chang-Huhn Lee ,  Mun-Mo Jeong ,  Wook-je Kim

IPC: H01L29/94 ,  H01L29/76 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC classification number: H01L29/6656 ,  H01L21/823468 ,  Y10S257/90 ,  Y10S438/978

Abstract: Embodiments of the invention provide a semiconductor device and a fabrication method for a semiconductor device that includes the processes of forming multiple gates on a silicon substrate, forming a gate spacer having a positive slope at the gate spacer edge, depositing a polysilicon layer on the silicon substrate between the gates, etching a portion of the polysilicon layer to form an opening exposing a portion of the silicon substrate, and forming an inter-insulation layer to the exposed portion of the silicon substrate to fill the opening. Using an annealing process applied to a layer in the gate spacer, the etch selectivity can be selectively controlled and consequently, the degree of slope at the gate spacer edge is predetermined.

Abstract translation: 本发明的实施例提供一种用于半导体器件的半导体器件和制造方法，其包括在硅衬底上形成多个栅极的工艺，在栅极间隔物边缘处形成具有正斜率的栅极间隔物，在硅上沉积多晶硅层 蚀刻多晶硅层的一部分以形成露出硅衬底的一部分的开口，以及形成绝缘层到硅衬底的暴露部分以填充开口。 使用施加到栅极间隔物中的层的退火工艺，可以选择性地控制蚀刻选择性，因此预定栅极间隔物边缘处的斜率。

公开(公告)号：US06969673B2

公开(公告)日：2005-11-29

申请号：US10631456

申请日：2003-07-30

Applicant: Chang-Huhn Lee ,  Mun-Mo Jeong ,  Wook-je Kim

Inventor： Chang-Huhn Lee ,  Mun-Mo Jeong ,  Wook-je Kim

IPC: H01L21/336 ,  H01L21/8234 ,  H01L21/3205

CPC classification number: H01L29/6656 ,  H01L21/823468 ,  Y10S257/90 ,  Y10S438/978

Abstract: Embodiments of the invention provide a semiconductor device and a fabrication method for a semiconductor device that includes the processes of forming multiple gates on a silicon substrate, forming a gate spacer having a positive slope at the gate spacer edge, depositing a polysilicon layer on the silicon substrate between the gates, etching a portion of the polysilicon layer to form an opening exposing a portion of the silicon substrate, and forming an inter-insulation layer to the exposed portion of the silicon substrate to fill the opening. Using an annealing process applied to a layer in the gate spacer, the etch selectivity can be selectively controlled and consequently, the degree of slope at the gate spacer edge is predetermined.

Abstract translation: 本发明的实施例提供一种用于半导体器件的半导体器件和制造方法，其包括在硅衬底上形成多个栅极的工艺，在栅极间隔物边缘处形成具有正斜率的栅极间隔物，在硅上沉积多晶硅层 蚀刻多晶硅层的一部分以形成露出硅衬底的一部分的开口，以及形成绝缘层到硅衬底的暴露部分以填充开口。 使用施加到栅极间隔物中的层的退火工艺，可以选择性地控制蚀刻选择性，因此预定栅极间隔物边缘处的斜率。

公开(公告)号：US08009895B2

公开(公告)日：2011-08-30

申请号：US11618360

申请日：2006-12-29

Applicant: Chang-Huhn Lee ,  Seok-Woo Hong

Inventor： Chang-Huhn Lee ,  Seok-Woo Hong

IPC: G06K9/00

CPC classification number: G06T7/0004 ,  G06T2207/30148

Abstract: A semiconductor wafer analysis system is provided. In an embodiment, the semiconductor wafer analysis system includes a tester to test semiconductor wafers manufactured by at least one manufacturing facility, a wafer map generation module to generate wafer maps on the basis of the test results from the tester, and a wafer analysis module. The wafer analysis module may include a data generation module that divides each wafer map into a plurality of defect analysis regions and generates feature vectors representing the semiconductor wafers, and an operation module that statistically analyzes the feature vectors.

Abstract translation: 提供半导体晶片分析系统。 在一个实施例中，半导体晶片分析系统包括测试器，用于测试由至少一个制造设备制造的半导体晶片，晶片图生成模块，以基于来自测试器的测试结果生成晶片图，以及晶片分析模块。 晶片分析模块可以包括将每个晶片图划分成多个缺陷分析区域并产生表示半导体晶片的特征向量的数据生成模块，以及统计分析特征向量的操作模块。

公开(公告)号：US07473954B2

公开(公告)日：2009-01-06

申请号：US11249097

申请日：2005-10-11

Applicant: Mun-Mo Jeong ,  Chang-Huhn Lee ,  Makoto Yoshida

Inventor： Mun-Mo Jeong ,  Chang-Huhn Lee ,  Makoto Yoshida

IPC: H01L29/94

CPC classification number: H01L27/10855 ,  H01L27/10814 ,  H01L27/10885

Abstract: A semiconductor device with a bitline structure has a stud type capping layer. A method of fabricating the same achieves sufficient process margins and reduces parasitic capacitance.The device may include an insulating film formed on a semiconductor substrate and having a bitline contact and a groove-shaped bitline pattern, a bitline formed on the bitline contact and on a portion of the bitline pattern and that is surrounded by the insulating film, and a bitline capping layer formed on the bitline within the bitline pattern and the insulating film that protrudes from the insulating film. A protruded portion of the bitline capping layer is wider than a width of the bitline.

Abstract translation: 具有位线结构的半导体器件具有螺柱型封盖层。 其制造方法实现了足够的工艺裕度并降低了寄生电容。 该器件可以包括形成在半导体衬底上并且具有位线接触和凹槽形位线图案的绝缘膜，形成在位线接触上的位线和位线图案的一部分并被绝缘膜包围的位线，以及 在位线图案内的位线上形成的位线封盖层和从绝缘膜突出的绝缘膜。 位线封盖层的突出部分宽于位线的宽度。

公开(公告)号：US07217618B2

公开(公告)日：2007-05-15

申请号：US10678530

申请日：2003-10-03

Applicant: Chang-Huhn Lee ,  Mun-Mo Jeong

Inventor： Chang-Huhn Lee ,  Mun-Mo Jeong

IPC: H01L21/8242

CPC classification number: H01L28/91 ,  H01L21/31116 ,  H01L27/10814 ,  H01L27/10852 ,  H01L27/10855 ,  H01L27/10885

Abstract: A semiconductor device and method for fabricating same according to an embodiment of the invention includes: preparing a semiconductor substrate having a first contact pad and a second contact pad; forming a first insulating film on the substrate; etching the first insulating film to form a groove-shaped bit line pattern and a contact exposing the first contact pad and the second contact pad, respectively; simultaneously forming a contact plug and a bit line in the contact and the bit line pattern, respectively, the contact plug and the bitline having upper surfaces that are coplanar; and forming a bottom electrode for a capacitor that is connected to the first contact pad.

Abstract translation: 根据本发明实施例的半导体器件及其制造方法包括：制备具有第一接触焊盘和第二接触焊盘的半导体衬底; 在所述基板上形成第一绝缘膜; 蚀刻第一绝缘膜以形成槽状位线图案和分别暴露第一接触焊盘和第二接触焊盘的接触; 同时分别在触点和位线图案中形成接触插塞和位线，接触插塞和具有共面的上表面的位线; 以及形成用于连接到第一接触焊盘的电容器的底部电极。

公开(公告)号：US20060027852A1

公开(公告)日：2006-02-09

申请号：US11249097

申请日：2005-10-11

Applicant: Mun-Mo Jeong ,  Chang-Huhn Lee ,  Makoto Yoshida

Inventor： Mun-Mo Jeong ,  Chang-Huhn Lee ,  Makoto Yoshida

IPC: H01L29/94 ,  H01L29/00

CPC classification number: H01L27/10855 ,  H01L27/10814 ,  H01L27/10885

Abstract: A semiconductor device with a bitline structure has a stud type capping layer. A method of fabricating the same achieves sufficient process margins and reduces parasitic capacitance. The device may include an insulating film formed on a semiconductor substrate and having a bitline contact and a groove-shaped bitline pattern, a bitline formed on the bitline contact and on a portion of the bitline pattern and that is surrounded by the insulating film, and a bitline capping layer formed on the bitline within the bitline pattern and the insulating film that protrudes from the insulating film. A protruded portion of the bitline capping layer is wider than a width of the bitline.

公开(公告)号：US06982199B2

公开(公告)日：2006-01-03

申请号：US10636131

申请日：2003-08-06

Applicant: Mun-Mo Jeong ,  Chang-Huhn Lee ,  Makoto Yoshida

Inventor： Mun-Mo Jeong ,  Chang-Huhn Lee ,  Makoto Yoshida

IPC: H01L21/8242

CPC classification number: H01L27/10855 ,  H01L27/10814 ,  H01L27/10885

Abstract: A semiconductor device with a bitline structure has a stud type capping layer. A method of fabricating the same achieves sufficient process margins and reduces parasitic capacitance. The device may include an insulating film formed on a semiconductor substrate and having a bitline contact and a groove-shaped bitline pattern, a bitline formed on the bitline contact and on a portion of the bitline pattern and that is surrounded by the insulating film, and a bitline capping layer formed on the bitline within the bitline pattern and the insulating film that protrudes from the insulating film. A protruded portion of the bitline capping layer is wider than the width of the bitline.

Abstract translation: 具有位线结构的半导体器件具有螺柱型封盖层。 其制造方法实现了足够的工艺裕度并降低了寄生电容。 该器件可以包括形成在半导体衬底上并且具有位线接触和凹槽形位线图案的绝缘膜，形成在位线接触上的位线和位线图案的一部分并被绝缘膜包围的位线，以及 在位线图案内的位线上形成的位线封盖层和从绝缘膜突出的绝缘膜。 位线封盖层的突出部分比位线的宽度宽。

公开(公告)号：US07923323B2

公开(公告)日：2011-04-12

申请号：US12469422

申请日：2009-05-20

Applicant: Seok-Woo Hong ,  Chang-Huhn Lee ,  Jae-Hun Kim

Inventor： Seok-Woo Hong ,  Chang-Huhn Lee ,  Jae-Hun Kim

IPC: H01L21/8242

CPC classification number: H01L28/84 ,  H01L27/10852

Abstract: Disclosed is a metal capacitor including a lower electrode having hemispherical metal grains thereon. The metal capacitor includes a lower metal electrode containing Ti, hemispherical metal grains containing Pd and formed on the lower metal electrode containing Ti, a dielectric layer formed on the lower metal electrode containing Ti and the hemispherical metal grains containing Pd, and an upper metal electrode formed on the dielectric layer.

Abstract translation: 公开了一种金属电容器，其包括其上具有半球形金属颗粒的下电极。 金属电容器包括含有Ti的下部金属电极，形成在含有Ti的下部金属电极上形成的含有Pd的半球形金属颗粒，形成在含有Ti的下部金属电极上的介电层和包含Pd的半球状金属颗粒和上部金属电极 形成在电介质层上。